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Berrange" , John Snow , qemu-ppc@nongnu.org, Fabiano Rosas Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::932; envelope-from=alistair23@gmail.com; helo=mail-ua1-x932.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jul 25, 2024 at 3:56=E2=80=AFAM Thomas Huth wrot= e: > > The avocado test defined test functions for both, riscv32 and riscv64. > Since we can run the whole file with multiple targets in the new > framework, we can now consolidate the functions so we have to only > define one function per machine now. > > Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Alistair > --- > tests/avocado/riscv_opensbi.py | 63 -------------------------- > tests/functional/meson.build | 8 ++++ > tests/functional/test_riscv_opensbi.py | 36 +++++++++++++++ > 3 files changed, 44 insertions(+), 63 deletions(-) > delete mode 100644 tests/avocado/riscv_opensbi.py > create mode 100755 tests/functional/test_riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi= .py > deleted file mode 100644 > index bfff9cc3c3..0000000000 > --- a/tests/avocado/riscv_opensbi.py > +++ /dev/null > @@ -1,63 +0,0 @@ > -# OpenSBI boot test for RISC-V machines > -# > -# Copyright (c) 2022, Ventana Micro > -# > -# This work is licensed under the terms of the GNU GPL, version 2 or > -# later. See the COPYING file in the top-level directory. > - > -from avocado_qemu import QemuSystemTest > -from avocado_qemu import wait_for_console_pattern > - > -class RiscvOpenSBI(QemuSystemTest): > - """ > - :avocado: tags=3Daccel:tcg > - """ > - timeout =3D 5 > - > - def boot_opensbi(self): > - self.vm.set_console() > - self.vm.launch() > - wait_for_console_pattern(self, 'Platform Name') > - wait_for_console_pattern(self, 'Boot HART MEDELEG') > - > - def test_riscv32_spike(self): > - """ > - :avocado: tags=3Darch:riscv32 > - :avocado: tags=3Dmachine:spike > - """ > - self.boot_opensbi() > - > - def test_riscv64_spike(self): > - """ > - :avocado: tags=3Darch:riscv64 > - :avocado: tags=3Dmachine:spike > - """ > - self.boot_opensbi() > - > - def test_riscv32_sifive_u(self): > - """ > - :avocado: tags=3Darch:riscv32 > - :avocado: tags=3Dmachine:sifive_u > - """ > - self.boot_opensbi() > - > - def test_riscv64_sifive_u(self): > - """ > - :avocado: tags=3Darch:riscv64 > - :avocado: tags=3Dmachine:sifive_u > - """ > - self.boot_opensbi() > - > - def test_riscv32_virt(self): > - """ > - :avocado: tags=3Darch:riscv32 > - :avocado: tags=3Dmachine:virt > - """ > - self.boot_opensbi() > - > - def test_riscv64_virt(self): > - """ > - :avocado: tags=3Darch:riscv64 > - :avocado: tags=3Dmachine:virt > - """ > - self.boot_opensbi() > diff --git a/tests/functional/meson.build b/tests/functional/meson.build > index a2c0398b03..ebc6e2d1c6 100644 > --- a/tests/functional/meson.build > +++ b/tests/functional/meson.build > @@ -55,6 +55,14 @@ tests_ppc_thorough =3D [ > 'ppc_bamboo', > ] > > +tests_riscv32_quick =3D [ > + 'riscv_opensbi', > +] > + > +tests_riscv64_quick =3D [ > + 'riscv_opensbi', > +] > + > tests_s390x_thorough =3D [ > 's390x_ccw_virtio', > 's390x_topology', > diff --git a/tests/functional/test_riscv_opensbi.py b/tests/functional/te= st_riscv_opensbi.py > new file mode 100755 > index 0000000000..d077e40f42 > --- /dev/null > +++ b/tests/functional/test_riscv_opensbi.py > @@ -0,0 +1,36 @@ > +#!/usr/bin/env python3 > +# > +# OpenSBI boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from qemu_test import QemuSystemTest > +from qemu_test import wait_for_console_pattern > + > +class RiscvOpenSBI(QemuSystemTest): > + > + timeout =3D 5 > + > + def boot_opensbi(self): > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv_spike(self): > + self.set_machine('spike') > + self.boot_opensbi() > + > + def test_riscv_sifive_u(self): > + self.set_machine('sifive_u') > + self.boot_opensbi() > + > + def test_riscv_virt(self): > + self.set_machine('virt') > + self.boot_opensbi() > + > +if __name__ =3D=3D '__main__': > + QemuSystemTest.main() > -- > 2.45.2 > >