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From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	dbarboza@ventanamicro.com, Palmer Dabbelt <palmer@dabbelt.com>,
	Weiwei Li <liwei1518@gmail.com>,
	zhiwei_liu@linux.alibaba.com,
	 Alistair Francis <alistair.francis@wdc.com>,
	atishp@rivosinc.com, bmeng.cn@gmail.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/2] include: bitops: Add mask extract64/deposit64
Date: Wed, 7 Aug 2024 14:10:27 +1000	[thread overview]
Message-ID: <CAKmqyKPpw9zVTAzQHNCcNeoV11yCaz9NMEJ+w2TitqK_vEtR0A@mail.gmail.com> (raw)
In-Reply-To: <9da48ab0-d88e-4d80-aca6-79dfa083bb9b@linaro.org>

On Tue, Aug 6, 2024 at 5:32 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/5/24 14:33, Alistair Francis wrote:
> > Based on the RISC-V get_field() and set_field() macros add
> > mask_extract64() and mask_deposit64() bitop functions. These can extrac
> > and deposit values into fields using a bit field mask directly instead
> > of a length and shift.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >   include/qemu/bitops.h | 35 +++++++++++++++++++++++++++++++++++
> >   1 file changed, 35 insertions(+)
> >
> > diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
> > index 2c0a2fe751..dd26f4a6b5 100644
> > --- a/include/qemu/bitops.h
> > +++ b/include/qemu/bitops.h
> > @@ -409,6 +409,22 @@ static inline uint64_t extract64(uint64_t value, int start, int length)
> >       return (value >> start) & (~0ULL >> (64 - length));
> >   }
> >
> > +/**
> > + * mask_extract64:
> > + * @value: the value to extract the bit field from
> > + * @mask: the mask bit field to extract
> > + *
> > + * Extract from the 64 bit input @value the bit mask specified by the
> > + * @mask parameter, and return it. The value returned is shifted
> > + * so that only the bit field is returned.
> > + *
> > + * Returns: the value of the bit field extracted from the input value.
> > + */
> > +static inline uint64_t mask_extract64(uint64_t value, uint64_t mask)
> > +{
> > +    return (value & mask) / (mask & ~(mask << 1));
> > +}
>
> Adding these miss the point of using "standard" qemu operations.

My thinking is that if they are added then they become standard :)

At least then they are included in core code and easier for people to
understand.

>
> But if we were going to add this, avoid the division.
>
>   (value & mask) >> ctz64(mask)

Good point

Alistair

>
> I presume the original formulation is so that the macro can be used in the context of a
> compile-time constant.
>
>
> r~


  reply	other threads:[~2024-08-07  4:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-05  4:33 [PATCH 0/2] target/riscv: Convert RISC-V custom bitops to standard ones Alistair Francis
2024-08-05  4:33 ` [PATCH 1/2] include: bitops: Add mask extract64/deposit64 Alistair Francis
2024-08-06  7:29   ` Richard Henderson
2024-08-07  4:10     ` Alistair Francis [this message]
2024-08-05  4:33 ` [PATCH 2/2] target/riscv: Remove get_field and set_field Alistair Francis

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