From: Alistair Francis <alistair23@gmail.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Ved Shanbhogue <ved@rivosinc.com>,
Atish Patra <atishp@rivosinc.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior
Date: Fri, 11 Oct 2024 13:13:56 +1000 [thread overview]
Message-ID: <CAKmqyKPrHtsjAnc8kX__BeHvxoMvm+MmYLWSgh5TKdx0FE8o9A@mail.gmail.com> (raw)
In-Reply-To: <20240925115808.77874-3-cleger@rivosinc.com>
On Wed, Sep 25, 2024 at 9:58 PM Clément Léger <cleger@rivosinc.com> wrote:
>
> When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
> when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
> when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
> to VU from HS.
I don't see mret being mentioned in the spec. Where do you see that
V/SSTATUS.SDT should be cleared?
Alistair
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
> target/riscv/op_helper.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 6895c7596b..00b6f75102 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -287,6 +287,18 @@ target_ulong helper_sret(CPURISCVState *env)
> get_field(mstatus, MSTATUS_SPIE));
> mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> +
> + if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
> + if (riscv_has_ext(env, RVH)) {
> + target_ulong prev_vu = get_field(env->hstatus, HSTATUS_SPV) &&
> + prev_priv == PRV_U;
> + /* Returning to VU from HS, vsstatus.sdt = 0 */
> + if (!env->virt_enabled && prev_vu) {
> + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0);
> + }
> + }
> + mstatus = set_field(mstatus, MSTATUS_SDT, 0);
> + }
> if (env->priv_ver >= PRIV_VERSION_1_12_0) {
> mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> }
> @@ -297,7 +309,6 @@ target_ulong helper_sret(CPURISCVState *env)
> target_ulong hstatus = env->hstatus;
>
> prev_virt = get_field(hstatus, HSTATUS_SPV);
> -
> hstatus = set_field(hstatus, HSTATUS_SPV, 0);
>
> env->hstatus = hstatus;
> @@ -328,6 +339,22 @@ static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc,
> riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
> }
> }
> +static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus,
> + target_ulong prev_priv,
> + target_ulong prev_virt)
> +{
> + /* If returning to U, VS or VU, sstatus.sdt = 0 */
> + if (prev_priv == PRV_U || (prev_virt &&
> + (prev_priv == PRV_S || prev_priv == PRV_U))) {
> + mstatus = set_field(mstatus, MSTATUS_SDT, 0);
> + /* If returning to VU, vsstatus.sdt = 0 */
> + if (prev_virt && prev_priv == PRV_U) {
> + env->vsstatus = set_field(env->vsstatus, MSTATUS_SDT, 0);
> + }
> + }
> +
> + return mstatus;
> +}
>
> target_ulong helper_mret(CPURISCVState *env)
> {
> @@ -345,6 +372,9 @@ target_ulong helper_mret(CPURISCVState *env)
> mstatus = set_field(mstatus, MSTATUS_MPP,
> riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
> mstatus = set_field(mstatus, MSTATUS_MPV, 0);
> + if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
> + mstatus = ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt);
> + }
> if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
> mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
> }
> @@ -382,6 +412,9 @@ target_ulong helper_mnret(CPURISCVState *env)
> if (prev_priv < PRV_M) {
> env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false);
> }
> + if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
> + env->mstatus = ssdbltrp_mxret(env, env->mstatus, prev_priv, prev_virt);
> + }
>
> if (riscv_has_ext(env, RVH) && prev_virt) {
> riscv_cpu_swap_hypervisor_regs(env);
> --
> 2.45.2
>
>
next prev parent reply other threads:[~2024-10-11 3:15 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 11:57 [PATCH v2 0/8] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions Clément Léger
2024-09-25 11:57 ` [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling Clément Léger
2024-10-11 2:49 ` Alistair Francis
2024-09-25 11:58 ` [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior Clément Léger
2024-10-11 3:13 ` Alistair Francis [this message]
2024-10-11 18:52 ` Ved Shanbhogue
2024-10-17 4:36 ` Alistair Francis
2024-10-17 18:27 ` Ved Shanbhogue
2024-10-18 2:21 ` Alistair Francis
2024-10-18 7:02 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling Clément Léger
2024-10-11 3:22 ` Alistair Francis
2024-10-14 7:43 ` Clément Léger
2024-10-17 4:29 ` Alistair Francis
2024-10-17 7:45 ` Clément Léger
2024-10-18 2:25 ` Alistair Francis
2024-10-18 7:04 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch Clément Léger
2024-10-11 3:24 ` Alistair Francis
2024-10-14 7:43 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling Clément Léger
2024-10-11 3:30 ` Alistair Francis
2024-10-11 7:40 ` Clément Léger
2024-09-25 11:58 ` [PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Clément Léger
2024-09-25 11:58 ` [PATCH v2 7/8] target/riscv: Implement Smdbltrp behavior Clément Léger
2024-09-25 11:58 ` [PATCH v2 8/8] target/riscv: Add Smdbltrp ISA extension enable switch Clément Léger
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