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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e36; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jul 1, 2024 at 1:41=E2=80=AFPM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. > This is required as MMU address translations run in S-mode. > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei > --- > target/riscv/cpu_helper.c | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 6709622dd3..1af83a0a36 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env,= hwaddr *physical, > > CPUState *cs =3D env_cpu(env); > int va_bits =3D PGSHIFT + levels * ptidxbits + widened; > + int sxlen =3D 16UL << riscv_cpu_sxl(env); > + int sxlen_bytes =3D sxlen / 8; > > if (first_stage =3D=3D true) { > target_ulong mask, masked_msbs; > > - if (TARGET_LONG_BITS > (va_bits - 1)) { > - mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; > + if (sxlen > (va_bits - 1)) { > + mask =3D (1L << (sxlen - (va_bits - 1))) - 1; > } else { > mask =3D 0; > } > @@ -961,7 +963,7 @@ restart: > > int pmp_prot; > int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_add= r, > - sizeof(target_ulong), > + sxlen_bytes, > MMU_DATA_LOAD, PRV_S); > if (pmp_ret !=3D TRANSLATE_SUCCESS) { > return TRANSLATE_PMP_FAIL; > @@ -1113,7 +1115,7 @@ restart: > * it is no longer valid and we must re-walk the page table. > */ > MemoryRegion *mr; > - hwaddr l =3D sizeof(target_ulong), addr1; > + hwaddr l =3D sxlen_bytes, addr1; > mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, > false, MEMTXATTRS_UNSPECIFIED); > if (memory_region_is_ram(mr)) { > @@ -1126,6 +1128,11 @@ restart: > *pte_pa =3D pte =3D updated_pte; > #else > target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, update= d_pte); I think you missed removing this line Alistair > + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { > + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, pte, upd= ated_pte); > + } else { > + old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_pte); > + } > if (old_pte !=3D pte) { > goto restart; > } > -- > 2.43.0 > >