* [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-03 2:27 ` Alistair Francis
2024-07-01 3:37 ` [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
hw/riscv/boot.c | 35 ++++++++++++++++++++++-----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 47281ca853..1a2c1ff9e0 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
}
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
- hwaddr rom_size, uint32_t reset_vec_size,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base, hwaddr rom_size,
+ uint32_t reset_vec_size,
uint64_t kernel_entry)
{
+ struct fw_dynamic_info32 dinfo32;
struct fw_dynamic_info dinfo;
size_t dinfo_len;
- if (sizeof(dinfo.magic) == 4) {
- dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
- dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
- dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
- dinfo.next_addr = cpu_to_le32(kernel_entry);
+ if (riscv_is_32bit(harts)) {
+ dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
+ dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo32.next_addr = cpu_to_le32(kernel_entry);
+ dinfo32.options = 0;
+ dinfo32.boot_hart = 0;
+ dinfo_len = sizeof(dinfo32);
} else {
dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
dinfo.next_addr = cpu_to_le64(kernel_entry);
+ dinfo.options = 0;
+ dinfo.boot_hart = 0;
+ dinfo_len = sizeof(dinfo);
}
- dinfo.options = 0;
- dinfo.boot_hart = 0;
- dinfo_len = sizeof(dinfo);
/**
* copy the dynamic firmware info. This information is specific to
@@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
exit(1);
}
- rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+ rom_add_blob_fixed_as("mrom.finfo",
+ riscv_is_32bit(harts) ?
+ (void *)&dinfo32 : (void *)&dinfo,
+ dinfo_len,
rom_base + reset_vec_size,
&address_space_memory);
}
@@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
+ riscv_rom_copy_firmware_info(machine, harts,
+ rom_base, rom_size,
+ sizeof(reset_vec),
kernel_entry);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index af5f923f54..5010c3eadb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
+ riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus,
+ memmap[SIFIVE_U_DEV_MROM].base,
memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index a2e4ae9cb0..806256d23f 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint64_t fdt_load_addr);
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
uint64_t kernel_entry);
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
index 1b749663dc..18664a174b 100644
--- a/include/hw/riscv/boot_opensbi.h
+++ b/include/hw/riscv/boot_opensbi.h
@@ -58,4 +58,33 @@ struct fw_dynamic_info {
target_long boot_hart;
};
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info32 {
+ /** Info magic */
+ int32_t magic;
+ /** Info version */
+ int32_t version;
+ /** Next booting stage address */
+ int32_t next_addr;
+ /** Next booting stage mode */
+ int32_t next_mode;
+ /** Options for OpenSBI library */
+ int32_t options;
+ /**
+ * Preferred boot HART id
+ *
+ * It is possible that the previous booting stage uses same link
+ * address as the FW_DYNAMIC firmware. In this case, the relocation
+ * lottery mechanism can potentially overwrite the previous booting
+ * stage while other HARTs are still running in the previous booting
+ * stage leading to boot-time crash. To avoid this boot-time crash,
+ * the previous booting stage can specify last HART that will jump
+ * to the FW_DYNAMIC firmware as the preferred boot HART.
+ *
+ * To avoid specifying a preferred boot HART, the previous booting
+ * stage can set it to -1UL which will force the FW_DYNAMIC firmware
+ * to use the relocation lottery mechanism.
+ */
+ int32_t boot_hart;
+};
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
2024-07-01 3:37 ` [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
@ 2024-07-03 2:27 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-07-03 2:27 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, TANG Tiancheng
On Mon, Jul 1, 2024 at 1:40 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
> of target_ulong.
>
> In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
> We create a fw_dynmaic_info32 struct for this purpose.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/boot.c | 35 ++++++++++++++++++++++-----------
> hw/riscv/sifive_u.c | 3 ++-
> include/hw/riscv/boot.h | 4 +++-
> include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++
> 4 files changed, 57 insertions(+), 14 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 47281ca853..1a2c1ff9e0 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
> rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
> }
>
> -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
> - hwaddr rom_size, uint32_t reset_vec_size,
> +void riscv_rom_copy_firmware_info(MachineState *machine,
> + RISCVHartArrayState *harts,
> + hwaddr rom_base, hwaddr rom_size,
> + uint32_t reset_vec_size,
> uint64_t kernel_entry)
> {
> + struct fw_dynamic_info32 dinfo32;
> struct fw_dynamic_info dinfo;
> size_t dinfo_len;
>
> - if (sizeof(dinfo.magic) == 4) {
> - dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
> - dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
> - dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
> - dinfo.next_addr = cpu_to_le32(kernel_entry);
> + if (riscv_is_32bit(harts)) {
> + dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
> + dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
> + dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
> + dinfo32.next_addr = cpu_to_le32(kernel_entry);
> + dinfo32.options = 0;
> + dinfo32.boot_hart = 0;
> + dinfo_len = sizeof(dinfo32);
> } else {
> dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
> dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
> dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
> dinfo.next_addr = cpu_to_le64(kernel_entry);
> + dinfo.options = 0;
> + dinfo.boot_hart = 0;
> + dinfo_len = sizeof(dinfo);
> }
> - dinfo.options = 0;
> - dinfo.boot_hart = 0;
> - dinfo_len = sizeof(dinfo);
>
> /**
> * copy the dynamic firmware info. This information is specific to
> @@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
> exit(1);
> }
>
> - rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
> + rom_add_blob_fixed_as("mrom.finfo",
> + riscv_is_32bit(harts) ?
> + (void *)&dinfo32 : (void *)&dinfo,
> + dinfo_len,
> rom_base + reset_vec_size,
> &address_space_memory);
> }
> @@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
> }
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> rom_base, &address_space_memory);
> - riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
> + riscv_rom_copy_firmware_info(machine, harts,
> + rom_base, rom_size,
> + sizeof(reset_vec),
> kernel_entry);
> }
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index af5f923f54..5010c3eadb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine)
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
>
> - riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
> + riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus,
> + memmap[SIFIVE_U_DEV_MROM].base,
> memmap[SIFIVE_U_DEV_MROM].size,
> sizeof(reset_vec), kernel_entry);
>
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index a2e4ae9cb0..806256d23f 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
> hwaddr rom_base, hwaddr rom_size,
> uint64_t kernel_entry,
> uint64_t fdt_load_addr);
> -void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
> +void riscv_rom_copy_firmware_info(MachineState *machine,
> + RISCVHartArrayState *harts,
> + hwaddr rom_base,
> hwaddr rom_size,
> uint32_t reset_vec_size,
> uint64_t kernel_entry);
> diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
> index 1b749663dc..18664a174b 100644
> --- a/include/hw/riscv/boot_opensbi.h
> +++ b/include/hw/riscv/boot_opensbi.h
> @@ -58,4 +58,33 @@ struct fw_dynamic_info {
> target_long boot_hart;
> };
>
> +/** Representation dynamic info passed by previous booting stage */
> +struct fw_dynamic_info32 {
> + /** Info magic */
> + int32_t magic;
> + /** Info version */
> + int32_t version;
> + /** Next booting stage address */
> + int32_t next_addr;
> + /** Next booting stage mode */
> + int32_t next_mode;
> + /** Options for OpenSBI library */
> + int32_t options;
> + /**
> + * Preferred boot HART id
> + *
> + * It is possible that the previous booting stage uses same link
> + * address as the FW_DYNAMIC firmware. In this case, the relocation
> + * lottery mechanism can potentially overwrite the previous booting
> + * stage while other HARTs are still running in the previous booting
> + * stage leading to boot-time crash. To avoid this boot-time crash,
> + * the previous booting stage can specify last HART that will jump
> + * to the FW_DYNAMIC firmware as the preferred boot HART.
> + *
> + * To avoid specifying a preferred boot HART, the previous booting
> + * stage can set it to -1UL which will force the FW_DYNAMIC firmware
> + * to use the relocation lottery mechanism.
> + */
> + int32_t boot_hart;
> +};
> #endif
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-01 3:37 ` [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-03 2:28 ` Alistair Francis
2024-07-01 3:37 ` [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..f65aa3dba7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2UL << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
2024-07-01 3:37 ` [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
@ 2024-07-03 2:28 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-07-03 2:28 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, TANG Tiancheng
On Mon, Jul 1, 2024 at 1:40 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Ensure pmp_size is correctly determined using mxl for RV32
> in RV64 QEMU.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9eea397e72..f65aa3dba7 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
> */
> pmp_size = -(addr | TARGET_PAGE_MASK);
> } else {
> - pmp_size = sizeof(target_ulong);
> + pmp_size = 2UL << riscv_cpu_mxl(env);
> }
> } else {
> pmp_size = size;
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-01 3:37 ` [PATCH 1/6] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-01 3:37 ` [PATCH 2/6] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-01 15:10 ` Philippe Mathieu-Daudé
2024-07-01 3:37 ` [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6fe0d712b4..36a712044a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -668,8 +668,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
#else
- return get_field(env->mstatus, MSTATUS64_SXL);
+ if (env->misa_mxl != MXL_RV32) {
+ return get_field(env->mstatus, MSTATUS64_SXL);
+ }
#endif
+ return MXL_RV32;
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
2024-07-01 3:37 ` [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-07-01 15:10 ` Philippe Mathieu-Daudé
2024-07-02 1:48 ` LIU Zhiwei
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-01 15:10 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng
Hi Tiancheng, Zhiwei,
On 1/7/24 05:37, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
> RV64 QEMU.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/cpu.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6fe0d712b4..36a712044a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -668,8 +668,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> #ifdef CONFIG_USER_ONLY
> return env->misa_mxl;
> #else
> - return get_field(env->mstatus, MSTATUS64_SXL);
> + if (env->misa_mxl != MXL_RV32) {
> + return get_field(env->mstatus, MSTATUS64_SXL);
> + }
> #endif
> + return MXL_RV32;
Can we simplify the previous TARGET_RISCV32 ifdef'ry?
> }
> #endif
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
2024-07-01 15:10 ` Philippe Mathieu-Daudé
@ 2024-07-02 1:48 ` LIU Zhiwei
0 siblings, 0 replies; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-02 1:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng
[-- Attachment #1: Type: text/plain, Size: 3683 bytes --]
On 2024/7/1 23:10, Philippe Mathieu-Daudé wrote:
> Hi Tiancheng, Zhiwei,
>
> On 1/7/24 05:37, LIU Zhiwei wrote:
>> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>>
>> Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
>> RV64 QEMU.
>>
>> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>> Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for
>> RV64")
>> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>> ---
>> target/riscv/cpu.h | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 6fe0d712b4..36a712044a 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -668,8 +668,11 @@ static inline RISCVMXL
>> riscv_cpu_sxl(CPURISCVState *env)
>> #ifdef CONFIG_USER_ONLY
>> return env->misa_mxl;
>> #else
>> - return get_field(env->mstatus, MSTATUS64_SXL);
>> + if (env->misa_mxl != MXL_RV32) {
>> + return get_field(env->mstatus, MSTATUS64_SXL);
>> + }
>> #endif
>> + return MXL_RV32;
>
> Can we simplify the previous TARGET_RISCV32 ifdef'ry?
I think you mean the TARGET_RISCV32 macro here:
#ifdef TARGET_RISCV32
#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
#else
static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
{
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
#else
return get_field(env->mstatus, MSTATUS64_SXL);
#endif
}
#endif
I think it is better to keep it here for better performance(as a constant).
If you mean whether we can simplify all the ifdef TARGET_RISCV32 in
target/riscv or hw/riscv, IMHO, it depends. I git grep the
TARGET_RISCV32 from target/riscv:
target/riscv/cpu-param.h:#elif defined(TARGET_RISCV32)
target/riscv/cpu.c:#ifdef TARGET_RISCV32
target/riscv/cpu.c:#if defined(TARGET_RISCV32)
target/riscv/cpu.h:#if defined(TARGET_RISCV32)
target/riscv/cpu.h:#ifdef TARGET_RISCV32
target/riscv/cpu.h:#if defined(TARGET_RISCV32)
target/riscv/cpu.h:#if defined(TARGET_RISCV32)
target/riscv/cpu.h:#ifdef TARGET_RISCV32
target/riscv/insn_trans/trans_rvzacas.c.inc:#ifdef TARGET_RISCV32
target/riscv/kvm/kvm-cpu.c:#if defined(TARGET_RISCV32)
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
target/riscv/translate.c:#ifdef TARGET_RISCV32
One case we can remove the TARGET_RISCV32 is in translate.c.
static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
{
if (!ctx->cfg_ptr->ext_zfinx) {
tcg_gen_mov_i64(cpu_fpr[reg_num], t);
return;
}
if (reg_num != 0) {
switch (get_xl(ctx)) {
case MXL_RV32:
#ifdef TARGET_RISCV32
tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
break;
#else
/* fall through */
case MXL_RV64:
tcg_gen_mov_i64(cpu_gpr[reg_num], t);
break;
#endif
default:
g_assert_not_reached();
}
}
}
We can simplify this code by tcg_gen_trunc_i64_tl.
One case we can't remove the TARGET_RISCV32 is in cpu.c, where we define
any or max cpu with the width depending on this macro.
I don't analyze all TARGET_RISCV32 using here. We will upstream a
standalone patch for validating all its using later.
Thanks,
Zhiwei
>
>> }
>> #endif
[-- Attachment #2: Type: text/html, Size: 5991 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (2 preceding siblings ...)
2024-07-01 3:37 ` [PATCH 3/6] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-03 2:33 ` Alistair Francis
2024-07-01 3:37 ` [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_helper.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6709622dd3..1af83a0a36 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int sxlen = 16UL << riscv_cpu_sxl(env);
+ int sxlen_bytes = sxlen / 8;
if (first_stage == true) {
target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ if (sxlen > (va_bits - 1)) {
+ mask = (1L << (sxlen - (va_bits - 1))) - 1;
} else {
mask = 0;
}
@@ -961,7 +963,7 @@ restart:
int pmp_prot;
int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
- sizeof(target_ulong),
+ sxlen_bytes,
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
return TRANSLATE_PMP_FAIL;
@@ -1113,7 +1115,7 @@ restart:
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
+ hwaddr l = sxlen_bytes, addr1;
mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
@@ -1126,6 +1128,11 @@ restart:
*pte_pa = pte = updated_pte;
#else
target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
+ } else {
+ old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ }
if (old_pte != pte) {
goto restart;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
2024-07-01 3:37 ` [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
@ 2024-07-03 2:33 ` Alistair Francis
2024-07-03 2:46 ` LIU Zhiwei
0 siblings, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2024-07-03 2:33 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, TANG Tiancheng
On Mon, Jul 1, 2024 at 1:41 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
> This is required as MMU address translations run in S-mode.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/cpu_helper.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 6709622dd3..1af83a0a36 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>
> CPUState *cs = env_cpu(env);
> int va_bits = PGSHIFT + levels * ptidxbits + widened;
> + int sxlen = 16UL << riscv_cpu_sxl(env);
> + int sxlen_bytes = sxlen / 8;
>
> if (first_stage == true) {
> target_ulong mask, masked_msbs;
>
> - if (TARGET_LONG_BITS > (va_bits - 1)) {
> - mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> + if (sxlen > (va_bits - 1)) {
> + mask = (1L << (sxlen - (va_bits - 1))) - 1;
> } else {
> mask = 0;
> }
> @@ -961,7 +963,7 @@ restart:
>
> int pmp_prot;
> int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
> - sizeof(target_ulong),
> + sxlen_bytes,
> MMU_DATA_LOAD, PRV_S);
> if (pmp_ret != TRANSLATE_SUCCESS) {
> return TRANSLATE_PMP_FAIL;
> @@ -1113,7 +1115,7 @@ restart:
> * it is no longer valid and we must re-walk the page table.
> */
> MemoryRegion *mr;
> - hwaddr l = sizeof(target_ulong), addr1;
> + hwaddr l = sxlen_bytes, addr1;
> mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
> false, MEMTXATTRS_UNSPECIFIED);
> if (memory_region_is_ram(mr)) {
> @@ -1126,6 +1128,11 @@ restart:
> *pte_pa = pte = updated_pte;
> #else
> target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
I think you missed removing this line
Alistair
> + if (riscv_cpu_sxl(env) == MXL_RV32) {
> + old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
> + } else {
> + old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
> + }
> if (old_pte != pte) {
> goto restart;
> }
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64
2024-07-03 2:33 ` Alistair Francis
@ 2024-07-03 2:46 ` LIU Zhiwei
0 siblings, 0 replies; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-03 2:46 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, TANG Tiancheng
On 2024/7/3 10:33, Alistair Francis wrote:
> On Mon, Jul 1, 2024 at 1:41 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>>
>> Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
>> This is required as MMU address translations run in S-mode.
>>
>> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
>> ---
>> target/riscv/cpu_helper.c | 15 +++++++++++----
>> 1 file changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 6709622dd3..1af83a0a36 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>>
>> CPUState *cs = env_cpu(env);
>> int va_bits = PGSHIFT + levels * ptidxbits + widened;
>> + int sxlen = 16UL << riscv_cpu_sxl(env);
>> + int sxlen_bytes = sxlen / 8;
>>
>> if (first_stage == true) {
>> target_ulong mask, masked_msbs;
>>
>> - if (TARGET_LONG_BITS > (va_bits - 1)) {
>> - mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
>> + if (sxlen > (va_bits - 1)) {
>> + mask = (1L << (sxlen - (va_bits - 1))) - 1;
>> } else {
>> mask = 0;
>> }
>> @@ -961,7 +963,7 @@ restart:
>>
>> int pmp_prot;
>> int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
>> - sizeof(target_ulong),
>> + sxlen_bytes,
>> MMU_DATA_LOAD, PRV_S);
>> if (pmp_ret != TRANSLATE_SUCCESS) {
>> return TRANSLATE_PMP_FAIL;
>> @@ -1113,7 +1115,7 @@ restart:
>> * it is no longer valid and we must re-walk the page table.
>> */
>> MemoryRegion *mr;
>> - hwaddr l = sizeof(target_ulong), addr1;
>> + hwaddr l = sxlen_bytes, addr1;
>> mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
>> false, MEMTXATTRS_UNSPECIFIED);
>> if (memory_region_is_ram(mr)) {
>> @@ -1126,6 +1128,11 @@ restart:
>> *pte_pa = pte = updated_pte;
>> #else
>> target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
> I think you missed removing this line
Good catch. We will fix this in v2 patch set.
Thanks,
Zhiwei
>
> Alistair
>
>> + if (riscv_cpu_sxl(env) == MXL_RV32) {
>> + old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
>> + } else {
>> + old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
>> + }
>> if (old_pte != pte) {
>> goto restart;
>> }
>> --
>> 2.43.0
>>
>>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (3 preceding siblings ...)
2024-07-01 3:37 ` [PATCH 4/6] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-01 3:37 ` [PATCH 6/6] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-02 14:18 ` [PATCH 0/6] target/riscv: Expose RV32 cpu to " Philippe Mathieu-Daudé
6 siblings, 0 replies; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1af83a0a36..88a187c10a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1673,6 +1673,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong tinst = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
+ int sxlen = 0;
+ int mxlen = 0;
if (!async) {
/* set tval to badaddr for traps with address information */
@@ -1799,7 +1801,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
+ sxlen = 16UL << riscv_cpu_sxl(env);
+ env->scause = cause | ((target_ulong)async << (sxlen - 1));
env->sepc = env->pc;
env->stval = tval;
env->htval = htval;
@@ -1830,7 +1833,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
- env->mcause = cause | ~(((target_ulong)-1) >> async);
+ mxlen = 16UL << riscv_cpu_mxl(env);
+ env->mcause = cause | ((target_ulong)async << (mxlen - 1));
env->mepc = env->pc;
env->mtval = tval;
env->mtval2 = mtval2;
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 6/6] target/riscv: Enable RV32 CPU support in RV64 QEMU
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (4 preceding siblings ...)
2024-07-01 3:37 ` [PATCH 5/6] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-07-01 3:37 ` LIU Zhiwei
2024-07-02 14:18 ` [PATCH 0/6] target/riscv: Expose RV32 cpu to " Philippe Mathieu-Daudé
6 siblings, 0 replies; 15+ messages in thread
From: LIU Zhiwei @ 2024-07-01 3:37 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng, Liu Zhiwei
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17 +++++++++++++----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index f688ffa7bc..5c1abb4b51 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml
# needed by boot.c
TARGET_NEED_FDT=y
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69a08e8c2c..58165901a2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -630,8 +630,10 @@ static void rv64e_bare_cpu_init(Object *obj)
riscv_cpu_set_misa_ext(env, RVE);
}
-#else /* !TARGET_RISCV64 */
+#endif /* !TARGET_RISCV64 */
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
static void rv32_base_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -2544,6 +2546,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
+#elif defined(TARGET_RISCV64)
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
@@ -2551,9 +2560,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
-#elif defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
--
2.43.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-07-01 3:37 [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (5 preceding siblings ...)
2024-07-01 3:37 ` [PATCH 6/6] target/riscv: Enable RV32 CPU support " LIU Zhiwei
@ 2024-07-02 14:18 ` Philippe Mathieu-Daudé
2024-07-03 2:35 ` Alistair Francis
6 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-07-02 14:18 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, TANG Tiancheng
Hi Zhiwei,
On 1/7/24 05:37, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
>
> - Run RV64 QEMU with RV32 CPU
> qemu-system-riscv64 -cpu rv32 -M virt -nographic \
> -kernel Image \
> -append "root=/dev/vda ro console=ttyS0" \
> -drive file=rootfs.ext2,format=raw,id=hd0 \
> -device virtio-blk-device,drive=hd0 -netdev user,id=net0 \
> -device virtio-net-device,netdev=net0
>
> OpenSBI v1.4
> QEMU emulator version 9.0.50 (v9.0.0-1132-g7799dc2e3b)
> [ 0.000000] Linux version 6.9.0 (developer@11109ca35736) (riscv32-unknown-linux-gnu-gcc (gc891d8dc23e-dirty) 13.2.0, GNU ld (GNU Binutils) 2.42) #3 SMP Fri May 31 08:42:15 UTC 2024
> [ 0.000000] random: crng init done
> [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
> [ 0.000000] Machine model: riscv-virtio,qemu
> [ 0.000000] SBI specification v2.0 detected
> [ 0.000000] SBI implementation ID=0x1 Version=0x10004
> [ 0.000000] SBI TIME extension detected
> [ 0.000000] SBI IPI extension detected
> [ 0.000000] SBI RFENCE extension detected
> [ 0.000000] SBI SRST extension detected
> [ 0.000000] SBI DBCN extension detected
> [ 0.000000] efi: UEFI not found.
> [ 0.000000] OF: reserved mem: 0x80000000..0x8003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000
> [ 0.000000] OF: reserved mem: 0x80040000..0x8004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000
> [ 0.000000] Zone ranges:
> [ 0.000000] Normal [mem 0x0000000080400000-0x0000000087ffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000080400000-0x0000000087ffffff]
> [ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x0000000087ffffff]
> [ 0.000000] On node 0, zone Normal: 1024 pages in unavailable ranges
> [ 0.000000] SBI HSM extension detected
> [ 0.000000] riscv: base ISA extensions acdfhim
> [ 0.000000] riscv: ELF capabilities acdfim
> [ 0.000000] percpu: Embedded 17 pages/cpu s37728 r8192 d23712 u69632
> [ 0.000000] Kernel command line: root=/dev/vda ro console=ttyS0
> [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
> [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 31465
> [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB)
> [ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB)
> [ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB)
> [ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xc7c00000 ( 124 MB)
> [ 0.000000] Memory: 95700K/126976K available (9090K kernel code, 8845K rwdata, 4096K rodata, 4231K init, 341K bss, 31276K reserved, 0K cma-reserved)
> ...
> Welcome to Buildroot
> buildroot login: root
> # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv32imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfa_zba_zbb_zbc_zbs_sstc
> mmu : sv32
Please provide an Avocado test (i.e. checking /proc/cpuinfo
contains "isa : rv32"). See for reference
tests/avocado/boot_linux_console.py.
Thanks!
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 0/6] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-07-02 14:18 ` [PATCH 0/6] target/riscv: Expose RV32 cpu to " Philippe Mathieu-Daudé
@ 2024-07-03 2:35 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-07-03 2:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: LIU Zhiwei, qemu-devel, qemu-riscv, palmer, alistair.francis,
dbarboza, liwei1518, bmeng.cn, TANG Tiancheng
On Wed, Jul 3, 2024 at 12:25 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Hi Zhiwei,
>
> On 1/7/24 05:37, LIU Zhiwei wrote:
> > From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> >
> > This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> > qemu-system-riscv64 can directly boot a RV32 Linux.
> >
> > This patch set has been tested with 6.9.0 Linux Image.
> >
> > - Run RV64 QEMU with RV32 CPU
> > qemu-system-riscv64 -cpu rv32 -M virt -nographic \
> > -kernel Image \
> > -append "root=/dev/vda ro console=ttyS0" \
> > -drive file=rootfs.ext2,format=raw,id=hd0 \
> > -device virtio-blk-device,drive=hd0 -netdev user,id=net0 \
> > -device virtio-net-device,netdev=net0
> >
> > OpenSBI v1.4
> > QEMU emulator version 9.0.50 (v9.0.0-1132-g7799dc2e3b)
> > [ 0.000000] Linux version 6.9.0 (developer@11109ca35736) (riscv32-unknown-linux-gnu-gcc (gc891d8dc23e-dirty) 13.2.0, GNU ld (GNU Binutils) 2.42) #3 SMP Fri May 31 08:42:15 UTC 2024
> > [ 0.000000] random: crng init done
> > [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80400000
> > [ 0.000000] Machine model: riscv-virtio,qemu
> > [ 0.000000] SBI specification v2.0 detected
> > [ 0.000000] SBI implementation ID=0x1 Version=0x10004
> > [ 0.000000] SBI TIME extension detected
> > [ 0.000000] SBI IPI extension detected
> > [ 0.000000] SBI RFENCE extension detected
> > [ 0.000000] SBI SRST extension detected
> > [ 0.000000] SBI DBCN extension detected
> > [ 0.000000] efi: UEFI not found.
> > [ 0.000000] OF: reserved mem: 0x80000000..0x8003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000
> > [ 0.000000] OF: reserved mem: 0x80040000..0x8004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000
> > [ 0.000000] Zone ranges:
> > [ 0.000000] Normal [mem 0x0000000080400000-0x0000000087ffffff]
> > [ 0.000000] Movable zone start for each node
> > [ 0.000000] Early memory node ranges
> > [ 0.000000] node 0: [mem 0x0000000080400000-0x0000000087ffffff]
> > [ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x0000000087ffffff]
> > [ 0.000000] On node 0, zone Normal: 1024 pages in unavailable ranges
> > [ 0.000000] SBI HSM extension detected
> > [ 0.000000] riscv: base ISA extensions acdfhim
> > [ 0.000000] riscv: ELF capabilities acdfim
> > [ 0.000000] percpu: Embedded 17 pages/cpu s37728 r8192 d23712 u69632
> > [ 0.000000] Kernel command line: root=/dev/vda ro console=ttyS0
> > [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
> > [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
> > [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 31465
> > [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
> > [ 0.000000] Virtual kernel memory layout:
> > [ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB)
> > [ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB)
> > [ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB)
> > [ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB)
> > [ 0.000000] lowmem : 0xc0000000 - 0xc7c00000 ( 124 MB)
> > [ 0.000000] Memory: 95700K/126976K available (9090K kernel code, 8845K rwdata, 4096K rodata, 4231K init, 341K bss, 31276K reserved, 0K cma-reserved)
> > ...
> > Welcome to Buildroot
> > buildroot login: root
> > # cat /proc/cpuinfo
> > processor : 0
> > hart : 0
> > isa : rv32imafdch_zicbom_zicboz_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfa_zba_zbb_zbc_zbs_sstc
> > mmu : sv32
>
> Please provide an Avocado test (i.e. checking /proc/cpuinfo
> contains "isa : rv32"). See for reference
> tests/avocado/boot_linux_console.py.
Awesome! Thanks for this, this is very exciting.
I agree we should add an Avacado test, that way this will be regularly
tested as it's something that seems prone to breakage.
Alistair
>
> Thanks!
>
^ permalink raw reply [flat|nested] 15+ messages in thread