From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: Anup Patel <anup.patel@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Mingwang Li <limingwang@huawei.com>,
"open list:Overall" <kvm@vger.kernel.org>,
libvir-list@redhat.com, Anup Patel <anup@brainfault.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wanbo13@huawei.com, Palmer Dabbelt <palmer@dabbelt.com>,
kvm-riscv@lists.infradead.org, wanghaibin.wang@huawei.com,
Alistair Francis <Alistair.Francis@wdc.com>,
fanliang@huawei.com, "Wubin \(H\)" <wu.wubin@huawei.com>
Subject: Re: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
Date: Tue, 11 Jan 2022 09:06:46 +1000 [thread overview]
Message-ID: <CAKmqyKPsSidxir_1fncugsmLK33aSbHk63MP0JnS3OJLvy65EA@mail.gmail.com> (raw)
In-Reply-To: <20220110013831.1594-6-jiangyifei@huawei.com>
On Mon, Jan 10, 2022 at 11:57 AM Yifei Jiang via <qemu-devel@nongnu.org> wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/kvm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 103 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 6d4df0ef6d..e695b91dc7 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -73,6 +73,14 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx
> } \
> } while(0)
>
> +#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
> + do { \
> + int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
> + if (ret) { \
> + return ret; \
> + } \
> + } while(0)
This fails checkpatch. I know there is lots of QEMU code like this,
but it probably should be `while (0)` to keep checkpatch happy.
Please run checkpatch on all the patches.
Alistair
next prev parent reply other threads:[~2022-01-10 23:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 1:38 [PATCH v4 00/12] Add riscv kvm accel support Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang via
2022-01-10 23:09 ` Alistair Francis
2022-01-12 8:04 ` Jiangyifei via
2022-01-10 1:38 ` [PATCH v4 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang via
2022-01-10 23:06 ` Alistair Francis [this message]
2022-01-12 8:01 ` Jiangyifei via
2022-01-10 1:38 ` [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang via
2022-01-11 0:27 ` Alistair Francis
2022-01-12 8:07 ` Jiangyifei via
2022-01-10 1:38 ` [PATCH v4 07/12] target/riscv: Support setting external interrupt " Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang via
2022-01-10 6:48 ` Alistair Francis
2022-01-10 1:38 ` [PATCH v4 09/12] target/riscv: Add host cpu type Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang via
2022-01-10 6:52 ` Alistair Francis
2022-01-10 1:38 ` [PATCH v4 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang via
2022-01-10 1:38 ` [PATCH v4 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang via
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