From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, ajones@ventanamicro.com
Subject: Re: [PATCH v3 4/6] target/riscv: Reset henvcfg to zero
Date: Thu, 15 Feb 2024 15:38:03 +1000 [thread overview]
Message-ID: <CAKmqyKPwegj6gYUdUrwH8qw99Ueme6KBF-eH88AAe2ZDhsA6Yw@mail.gmail.com> (raw)
In-Reply-To: <20240202152154.773253-5-dbarboza@ventanamicro.com>
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> From: Andrew Jones <ajones@ventanamicro.com>
>
> The hypervisor should decide what it wants to enable. Zero all
> configuration enable bits on reset.
>
> Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for
> svadu extension") missed one reference to 'hade'. Change it now.
>
> Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation")
> Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 3 +--
> target/riscv/csr.c | 2 +-
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 94843c4f6e..9045f87481 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj)
>
> env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
> (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
> - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
> - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
> + env->henvcfg = 0;
>
> /* Initialized default priorities of local interrupts. */
> for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d9a010387f..93f7bc2cb4 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2115,7 +2115,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> /*
> * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
> * henvcfg.stce is read_only 0 when menvcfg.stce = 0
> - * henvcfg.hade is read_only 0 when menvcfg.hade = 0
> + * henvcfg.adue is read_only 0 when menvcfg.adue = 0
> */
> *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) |
> env->menvcfg);
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2024-02-15 5:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 15:21 [PATCH v3 0/6] riscv: named features riscv,isa, 'svade' rework Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 2/6] target/riscv: add riscv,isa to named features Daniel Henrique Barboza
2024-02-02 15:21 ` [PATCH v3 3/6] target/riscv: add remaining " Daniel Henrique Barboza
2024-02-05 14:04 ` Andrew Jones
2024-02-15 4:20 ` Alistair Francis
2024-02-15 13:33 ` Conor Dooley
2024-02-15 14:13 ` Daniel Henrique Barboza
2024-02-15 14:39 ` Andrew Jones
2024-02-15 14:26 ` Andrew Jones
2024-02-15 16:34 ` Conor Dooley
2024-02-15 19:11 ` Andrew Jones
2024-02-15 19:59 ` Conor Dooley
2024-02-16 0:12 ` Alistair Francis
2024-02-16 15:08 ` Conor Dooley
2024-02-02 15:21 ` [PATCH v3 4/6] target/riscv: Reset henvcfg to zero Daniel Henrique Barboza
2024-02-15 5:38 ` Alistair Francis [this message]
2024-02-02 15:21 ` [PATCH v3 5/6] target/riscv: Gate hardware A/D PTE bit updating Daniel Henrique Barboza
2024-02-15 5:46 ` Alistair Francis
2024-02-02 15:21 ` [PATCH v3 6/6] target/riscv: Promote svade to a normal extension Daniel Henrique Barboza
2024-02-15 5:41 ` Alistair Francis
2024-02-15 9:52 ` [PATCH v3 0/6] riscv: named features riscv,isa, 'svade' rework Alistair Francis
2024-02-15 21:28 ` Daniel Henrique Barboza
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