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Sun, 15 Oct 2023 18:52:33 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Alistair Francis Date: Mon, 16 Oct 2023 11:52:07 +1000 Message-ID: Subject: Re: [RFC PATCH v3 27/78] target/riscv: add fallthrough pseudo-keyword To: Emmanouil Pitsidianakis Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "open list:RISC-V TCG CPUs" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Oct 2023 01:52:36 -0000 On Fri, Oct 13, 2023 at 6:52=E2=80=AFPM Emmanouil Pitsidianakis wrote: > > In preparation of raising -Wimplicit-fallthrough to 5, replace all > fall-through comments with the fallthrough attribute pseudo-keyword. > > Signed-off-by: Emmanouil Pitsidianakis Acked-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 2 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++++++++++----------- > target/riscv/translate.c | 4 ++-- > 3 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_= trans/trans_rvi.c.inc > index 25cb60558a..98dd2e3cf6 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -122,7 +122,7 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl, > > case TCG_COND_LTU: > invert =3D true; > - /* fallthrough */ > + fallthrough; > case TCG_COND_GEU: > { > TCGv tmp =3D tcg_temp_new(); > diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/ins= n_trans/trans_rvzce.c.inc > index 2d992e14c4..f0bcbb4f72 100644 > --- a/target/riscv/insn_trans/trans_rvzce.c.inc > +++ b/target/riscv/insn_trans/trans_rvzce.c.inc > @@ -125,37 +125,37 @@ static uint32_t decode_push_pop_list(DisasContext *= ctx, target_ulong rlist) > case 15: > reg_bitmap |=3D 1 << (X_Sn + 11) ; > reg_bitmap |=3D 1 << (X_Sn + 10) ; > - /* FALL THROUGH */ > + fallthrough; > case 14: > reg_bitmap |=3D 1 << (X_Sn + 9) ; > - /* FALL THROUGH */ > + fallthrough; > case 13: > reg_bitmap |=3D 1 << (X_Sn + 8) ; > - /* FALL THROUGH */ > + fallthrough; > case 12: > reg_bitmap |=3D 1 << (X_Sn + 7) ; > - /* FALL THROUGH */ > + fallthrough; > case 11: > reg_bitmap |=3D 1 << (X_Sn + 6) ; > - /* FALL THROUGH */ > + fallthrough; > case 10: > reg_bitmap |=3D 1 << (X_Sn + 5) ; > - /* FALL THROUGH */ > + fallthrough; > case 9: > reg_bitmap |=3D 1 << (X_Sn + 4) ; > - /* FALL THROUGH */ > + fallthrough; > case 8: > reg_bitmap |=3D 1 << (X_Sn + 3) ; > - /* FALL THROUGH */ > + fallthrough; > case 7: > reg_bitmap |=3D 1 << (X_Sn + 2) ; > - /* FALL THROUGH */ > + fallthrough; > case 6: > reg_bitmap |=3D 1 << X_S1 ; > - /* FALL THROUGH */ > + fallthrough; > case 5: > reg_bitmap |=3D 1 << X_S0; > - /* FALL THROUGH */ > + fallthrough; > case 4: > reg_bitmap |=3D 1 << xRA; > break; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f0be79bb16..c99e513221 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -446,7 +446,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg= _num) > return t; > } > #else > - /* fall through */ > + fallthrough; > case MXL_RV64: > return cpu_gpr[reg_num]; > #endif > @@ -516,7 +516,7 @@ static void gen_set_fpr_hs(DisasContext *ctx, int reg= _num, TCGv_i64 t) > tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); > break; > #else > - /* fall through */ > + fallthrough; > case MXL_RV64: > tcg_gen_mov_i64(cpu_gpr[reg_num], t); > break; > -- > 2.39.2 > >