From: Alistair Francis <alistair23@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Michael Clark" <mjc@sifive.com>
Subject: Re: [Qemu-devel] [PULL 0/7] riscv-pull queue
Date: Fri, 29 Jun 2018 07:52:59 -0700 [thread overview]
Message-ID: <CAKmqyKPy2=9QZ=Y7awAqnDMXSNTc3+bA+D4X7KxDO6Ge922MYA@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-HqcKC8bgUPrN5ZJ1v9+7PtdMazEj9gOfbG-Em14ScCA@mail.gmail.com>
On Fri, Jun 29, 2018 at 7:49 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 29 June 2018 at 15:27, Alistair Francis <alistair23@gmail.com> wrote:
>> On Fri, Jun 29, 2018 at 7:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> So the problem is that your key is using some algorithm
>>> that's too newfangled for my gpg to cope with...
>>
>> Hmm... I do use gpg2, but it's just an RSA2048 key.
>
> Philippe says it's ECDH NISTP-521...
>
>> Is it possible to update your GPG?
>
> I don't believe any gpg(1) supports that algorithm.
> I'm not really keen on moving to gpg2 because I hear bad
> things about it...
Ok, I'll generate a new non-ECC key today and send a new PR.
Alistair
>
> thanks
> -- PMM
next prev parent reply other threads:[~2018-06-29 14:53 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 17:44 [Qemu-devel] [PULL 0/7] riscv-pull queue Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 2/7] hw/riscv/sifive_e: Create a SiFive E " Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ Alistair Francis
2018-06-27 17:44 ` [Qemu-devel] [PULL 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device Alistair Francis
2018-06-28 16:52 ` [Qemu-devel] [PULL 0/7] riscv-pull queue Peter Maydell
2018-06-28 21:35 ` Philippe Mathieu-Daudé
2018-06-29 9:41 ` Peter Maydell
2018-06-29 14:13 ` Alistair Francis
2018-06-29 14:21 ` Peter Maydell
2018-06-29 14:27 ` Alistair Francis
2018-06-29 14:49 ` Peter Maydell
2018-06-29 14:52 ` Alistair Francis [this message]
2018-06-29 14:31 ` Philippe Mathieu-Daudé
2018-06-29 14:49 ` Daniel P. Berrangé
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