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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2a; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Jun 1, 2024 at 6:31=E2=80=AFAM Daniel Henrique Barboza wrote: > > The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the > 'compatible' property. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml > > Reported-by: Conor Dooley > Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to v= irt machine") > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 56d7e945c6..ac70993679 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -515,6 +515,9 @@ static void create_fdt_one_imsic(RISCVVirtState *s, h= waddr base_addr, > uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; > g_autofree uint32_t *imsic_cells =3D NULL; > g_autofree uint32_t *imsic_regs =3D NULL; > + static const char * const imsic_compat[2] =3D { > + "qemu,imsics", "riscv,imsics" > + }; > > imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); > imsic_regs =3D g_new0(uint32_t, socket_count * 4); > @@ -541,7 +544,10 @@ static void create_fdt_one_imsic(RISCVVirtState *s, = hwaddr base_addr, > imsic_name =3D g_strdup_printf("/soc/interrupt-controller@%lx", > (unsigned long)base_addr); > qemu_fdt_add_subnode(ms->fdt, imsic_name); > - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,im= sics"); > + qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", > + (char **)&imsic_compat, > + ARRAY_SIZE(imsic_compat)); > + > qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", > FDT_IMSIC_INT_CELLS); > qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, = 0); > -- > 2.45.1 > >