From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 2/4] hw/riscv: Return the end address of the loaded firmware
Date: Fri, 9 Oct 2020 15:09:58 -0700 [thread overview]
Message-ID: <CAKmqyKPzzpCNXfU9Q4HRpZc694vHP2Ayy4Otx4VD0sTYFWKVkA@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmVdv_7onVjDes6_Tw0h2F4FqVnuiofFkRm5tHLO4GE6Kg@mail.gmail.com>
On Fri, Oct 9, 2020 at 3:14 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Oct 2, 2020 at 11:42 PM Alistair Francis
> <alistair.francis@wdc.com> wrote:
>
> It merits some commit message to explain why the return value of
> riscv_load_firmware() was changed from firmware entry address to
> firmware end address.
Done.
Alistair
>
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > include/hw/riscv/boot.h | 8 ++++----
> > hw/riscv/boot.c | 28 +++++++++++++++++-----------
> > 2 files changed, 21 insertions(+), 15 deletions(-)
> >
>
> Regards,
> Bin
next prev parent reply other threads:[~2020-10-09 22:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-02 15:31 [PATCH v1 0/4] Allow loading a no MMU kernel Alistair Francis
2020-10-02 15:31 ` [PATCH v1 1/4] hw/riscv: sifive_u: Allow specifying the CPU Alistair Francis
2020-10-09 10:03 ` Bin Meng
2020-10-02 15:31 ` [PATCH v1 2/4] hw/riscv: Return the end address of the loaded firmware Alistair Francis
2020-10-09 10:13 ` Bin Meng
2020-10-09 22:09 ` Alistair Francis [this message]
2020-10-02 15:31 ` [PATCH v1 3/4] hw/riscv: Add a riscv_is_32_bit() function Alistair Francis
2020-10-02 15:31 ` [PATCH v1 4/4] hw/riscv: Load the kernel after the firmware Alistair Francis
2020-10-09 10:29 ` Bin Meng
2020-10-13 15:55 ` Alistair Francis
2020-10-09 9:53 ` [PATCH v1 0/4] Allow loading a no MMU kernel Bin Meng
2020-10-09 22:32 ` Alistair Francis
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