Re: [Qemu-devel] [PATCH v4 5/5] target/mips: Refactor and fix INSERT.<B|H|W|D> instructions

[Aleksandar Markovic <aleksandar.m.mail@gmail.com>]

On Apr 2, 2019 3:49 PM, "Mateja Marjanovic" <mateja.marjanovic@rt-rk.com>
wrote:
>
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> The old version of the helper for the INSERT.<B|H|W|D> MSA instructions
> has been replaced with four helpers that don't use switch, and change
> the endianness of the given index, when executed on a big endian host.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> ---

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

I'll do minor corrections (resulting from this mail thread discussion)
while applying to my pull request.

>  target/mips/helper.h     |  5 +++-
>  target/mips/msa_helper.c | 65
++++++++++++++++++++++++++++++++++++------------
>  target/mips/translate.c  | 19 +++++++++++++-
>  3 files changed, 71 insertions(+), 18 deletions(-)
>
> diff --git a/target/mips/helper.h b/target/mips/helper.h
> index 8b6703c..82f6a40 100644
> --- a/target/mips/helper.h
> +++ b/target/mips/helper.h
> @@ -875,7 +875,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32,
i32)
>  DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
>
> -DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
>  DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
> @@ -942,6 +941,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
>  DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
>  DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
>  DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
> +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
> +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
> +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
> +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
>
>  DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
>  DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index d5bf4dc..d5c3842 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -1323,28 +1323,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env,
uint32_t rd,
>      env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
>  }
>
> -void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> +void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
>                            uint32_t rs_num, uint32_t n)
>  {
>      wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
>      target_ulong rs = env->active_tc.gpr[rs_num];
> +    n %= 16;
> +#if defined(HOST_WORDS_BIGENDIAN)
> +    if (n < 8) {
> +        n = 8 - n - 1;
> +    } else {
> +        n = 24 - n - 1;
> +    }
> +#endif
> +    pwd->b[n] = (int8_t)rs;
> +}
>
> -    switch (df) {
> -    case DF_BYTE:
> -        pwd->b[n] = (int8_t)rs;
> -        break;
> -    case DF_HALF:
> -        pwd->h[n] = (int16_t)rs;
> -        break;
> -    case DF_WORD:
> -        pwd->w[n] = (int32_t)rs;
> -        break;
> -    case DF_DOUBLE:
> -        pwd->d[n] = (int64_t)rs;
> -        break;
> -    default:
> -        assert(0);
> +void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
> +                          uint32_t rs_num, uint32_t n)
> +{
> +    wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> +    target_ulong rs = env->active_tc.gpr[rs_num];
> +    n %= 8;
> +#if defined(HOST_WORDS_BIGENDIAN)
> +    if (n < 4) {
> +        n = 4 - n - 1;
> +    } else {
> +        n = 12 - n - 1;
> +    }
> +#endif
> +    pwd->h[n] = (int16_t)rs;
> +}
> +
> +void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
> +                          uint32_t rs_num, uint32_t n)
> +{
> +    wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> +    target_ulong rs = env->active_tc.gpr[rs_num];
> +    n %= 4;
> +#if defined(HOST_WORDS_BIGENDIAN)
> +    if (n < 2) {
> +        n = 2 - n - 1;
> +    } else {
> +        n = 6 - n - 1;
>      }
> +#endif
> +    pwd->w[n] = (int32_t)rs;
> +}
> +
> +void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
> +                          uint32_t rs_num, uint32_t n)
> +{
> +    wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> +    target_ulong rs = env->active_tc.gpr[rs_num];
> +    n %= 2;
> +    pwd->d[n] = (int64_t)rs;
>  }
>
>  void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 72ed0a8..64587c4 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -29446,7 +29446,24 @@ static void gen_msa_elm_df(CPUMIPSState *env,
DisasContext *ctx, uint32_t df,
>              }
>              break;
>          case OPC_INSERT_df:
> -            gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
> +            switch (df) {
> +            case DF_BYTE:
> +                gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
> +                break;
> +            case DF_HALF:
> +                gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
> +                break;
> +            case DF_WORD:
> +                gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
> +                break;
> +#if defined(TARGET_MIPS64)
> +            case DF_DOUBLE:
> +                gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
> +                break;
> +#endif
> +            default:
> +                assert(0);
> +            }
>              break;
>          }
>          break;
> --
> 2.7.4
>
>