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X-Received-From: 2607:f8b0:4864:20::244 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Richard Henderson , QEMU Developers , Pavel Dovgalyuk , Igor Mammedov , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Nov 24, 2019 at 6:03 AM Michael Rolnik wrote: > > Signed-off-by: Michael Rolnik > --- > target/avr/translate.c | 132 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 132 insertions(+) > create mode 100644 target/avr/translate.c > > diff --git a/target/avr/translate.c b/target/avr/translate.c > new file mode 100644 > index 0000000000..53c9892a60 > --- /dev/null > +++ b/target/avr/translate.c > @@ -0,0 +1,132 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/qemu-print.h" > +#include "tcg/tcg.h" > +#include "cpu.h" > +#include "exec/exec-all.h" > +#include "disas/disas.h" > +#include "tcg-op.h" > +#include "exec/cpu_ldst.h" > +#include "exec/helper-proto.h" > +#include "exec/helper-gen.h" > +#include "exec/log.h" > +#include "exec/gdbstub.h" > +#include "exec/translator.h" > +#include "exec/gen-icount.h" > + > +/* > + * Define if you want a BREAK instruction translated to a breakpoint > + * Active debugging connection is assumed > + * This is for > + * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests > + * tests > + */ > +#undef BREAKPOINT_ON_BREAK > + > +static TCGv cpu_pc; > + > +static TCGv cpu_Cf; > +static TCGv cpu_Zf; > +static TCGv cpu_Nf; > +static TCGv cpu_Vf; > +static TCGv cpu_Sf; > +static TCGv cpu_Hf; > +static TCGv cpu_Tf; > +static TCGv cpu_If; > + > +static TCGv cpu_rampD; > +static TCGv cpu_rampX; > +static TCGv cpu_rampY; > +static TCGv cpu_rampZ; > + > +static TCGv cpu_r[NO_CPU_REGISTERS]; > +static TCGv cpu_eind; > +static TCGv cpu_sp; > + > +static TCGv cpu_skip; > + > +static const char reg_names[NO_CPU_REGISTERS][8] = { > + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", > + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", > + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", > + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", > +}; > +#define REG(x) (cpu_r[x]) > + > +enum { > + DISAS_EXIT = DISAS_TARGET_0, /* We want return to the cpu main loop. */ > + DISAS_LOOKUP = DISAS_TARGET_1, /* We have a variable condition exit. */ > + DISAS_CHAIN = DISAS_TARGET_2, /* We have a single condition exit. */ > +}; > + > +typedef struct DisasContext DisasContext; > + > +/* This is the state at translation time. */ > +struct DisasContext { > + TranslationBlock *tb; > + > + CPUAVRState *env; > + CPUState *cs; > + > + target_long npc; > + uint32_t opcode; > + > + /* Routine used to access memory */ > + int memidx; > + int bstate; > + int singlestep; > + > + TCGv skip_var0; > + TCGv skip_var1; > + TCGCond skip_cond; > + bool free_skip_var0; This set of four lines are by far the hardest to connect to the documentation. Please add before them a sizable comment with explanations for: - the reson these variables are introduced - why are they here (part of DisasContext) - what they affect - summary of the way they work Perhaps add comments to other places where "skip"-related data fields are introduced. (I believe the implementation is correct, but it is extremely hard to the reader to reverse-engineer the intentions) Yours, Aleksandar > +}; > + > +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); } > +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); } > +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; } > +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; } > + > +static uint16_t next_word(DisasContext *ctx) > +{ > + return cpu_lduw_code(ctx->env, ctx->npc++ * 2); > +} > + > +static int append_16(DisasContext *ctx, int x) > +{ > + return x << 16 | next_word(ctx); > +} > + > + > +static bool avr_have_feature(DisasContext *ctx, int feature) > +{ > + if (!avr_feature(ctx->env, feature)) { > + gen_helper_unsupported(cpu_env); > + ctx->bstate = DISAS_NORETURN; > + return false; > + } > + return true; > +} > + > +static bool decode_insn(DisasContext *ctx, uint16_t insn); > +#include "decode_insn.inc.c" > + > -- > 2.17.2 (Apple Git-113) >