From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FEFBC432C0 for ; Sun, 1 Dec 2019 00:51:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3C732082E for ; Sun, 1 Dec 2019 00:51:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="plr4zriI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E3C732082E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibDSj-0002RN-0J for qemu-devel@archiver.kernel.org; Sat, 30 Nov 2019 19:51:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55465) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibDS0-00022Y-9J for qemu-devel@nongnu.org; Sat, 30 Nov 2019 19:51:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibDRw-0006YQ-I7 for qemu-devel@nongnu.org; Sat, 30 Nov 2019 19:51:00 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:36078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibDRw-0006Wl-9d for qemu-devel@nongnu.org; Sat, 30 Nov 2019 19:50:56 -0500 Received: by mail-oi1-x243.google.com with SMTP id c16so7094623oic.3 for ; Sat, 30 Nov 2019 16:50:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=oFEKs4OhPbD8A0+I+eUJmtT596PM3JFkbOBOnU8AC4U=; b=plr4zriIHrA9hGVHRrlaRlhUynPuxjbfPeixdaEXO9UnTpMvaMChEE3EBwhANDxKa5 0DcrlGP6zRL86CLwOHNedS2ZMAlEh3hFvIz/M4TMs3dZb805p5dQWmmnTtO89uOXYoiW IZllZrr7KBFjO1J1zqIechFjStsXmsgFpSKGLIJZ+3RJs5Yi8e4Rc2QWVNi6juZSve4o 9QG0iNxeK/Pp9kwNxHsKwo5I9OdNkDAIw6NV1O1o0+UgOP5id5F02c/ZTG8C60H0sj5O KxTF4IUTSBmGn9RHwOEa+2y90+s6y+eMoS0UwleDH+pw4bPfocbpQF8w2/8C7A7GJlP1 GiMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=oFEKs4OhPbD8A0+I+eUJmtT596PM3JFkbOBOnU8AC4U=; b=hlvKMlv5QMPBYD7k3xx7/i3AzMXMQJPWgZgjdav/pjcYQmHU4LgQVYTEAMDOY7FRHp CkgG5v5kTXXY57SKXT1rzt4IRkPQxGikeOJBfhsUDJuFZ4B2UXRHUeOUeVs4gRupM5Jb C2JjhRB1584IqbqXFGDzGlaO4JKmICc2yf2Zz7kdX2VcVvmrI7Yt7xTAXK9xXyWGN+V9 PtSFhrnVJQWWyjI0X3rttBdnprCJSOcCdkGHpZLJEcpB5kwsi2z8QDrwflRKnqrgFnDN 6WGKk7QHXakcCdS7QGI3V7U0TZMJ78avrJqTg2H9fsbq7EGIMXLfb03OfO3atwp3eo+z mrbA== X-Gm-Message-State: APjAAAXjxqu5B5iA4N67piMqg+dT28TIEYch8MfwHkH47W4/VnqrgCmb l4BNd270tHyf9X0eBoWUjB2me9XrGgZOcKjM2KY= X-Google-Smtp-Source: APXvYqxKqzYZh0l8hq6cCD1nz0xx8jWoisS9SyNxR6hppQ06jCnqRTriW0buesLjnBrDpCRAbzXKDDQGC/vAQtk066o= X-Received: by 2002:aca:bd85:: with SMTP id n127mr9733010oif.136.1575161455288; Sat, 30 Nov 2019 16:50:55 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a05:6830:1391:0:0:0:0 with HTTP; Sat, 30 Nov 2019 16:50:54 -0800 (PST) In-Reply-To: References: <20191029212430.20617-1-mrolnik@gmail.com> <20191029212430.20617-2-mrolnik@gmail.com> From: Aleksandar Markovic Date: Sun, 1 Dec 2019 01:50:54 +0100 Message-ID: Subject: Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic To: Michael Rolnik Content-Type: multipart/alternative; boundary="00000000000001a705059899dbcc" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Sarah Harris , Richard Henderson , QEMU Developers , Pavel Dovgalyuk , Igor Mammedov , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000001a705059899dbcc Content-Type: text/plain; charset="UTF-8" On Saturday, November 30, 2019, Michael Rolnik wrote: > Aleksandar. > > if download AVR specs you can see that some cores implement some > instructions and some don't. > We could go other way, just implement all of them regardless of what is > supported and what is not and hope that executed elf contains only > supported ones. > > The current way is much better than a single "super-core", absolutely. OK, sorry, it was quite unresonable from me to request from you checking 400+ (or perhaps 500+) existing AVR microcontroller specifications for all features (boy, these numbers are staggering). But, in future, while extending or revising AVR support, please consider specification sheets as really the only valid reference. Have a great weekend! Aleksandar Regards, > Michael Rolnik > > > > On Sat, Nov 30, 2019 at 6:22 PM Aleksandar Markovic < > aleksandar.m.mail@gmail.com> wrote: > >> >> >> On Saturday, November 23, 2019, Michael Rolnik wrote: >> >>> On Fri, Nov 22, 2019 at 7:12 PM Aleksandar Markovic >>> wrote: >>> > >>> > > + >>> > > +static void avr_avr1_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > +} >>> > > + >>> > > +static void avr_avr2_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > +} >>> > > + >>> > > +static void avr_avr25_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > +} >>> > > + >>> > > +static void avr_avr3_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > +} >>> > > + >>> > > +static void avr_avr31_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > +} >>> > > + >>> > > +static void avr_avr35_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > +} >>> > > + >>> > > +static void avr_avr4_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > +} >>> > > + >>> > > +static void avr_avr5_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > +} >>> > > + >>> > > +static void avr_avr51_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > +} >>> > > + >>> > > +static void avr_avr6_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > +} >>> > > + >>> > > +static void avr_xmega2_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > + avr_set_feature(env, AVR_FEATURE_RMW); >>> > > +} >>> > > + >>> > > +static void avr_xmega4_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > + avr_set_feature(env, AVR_FEATURE_RMW); >>> > > +} >>> > > + >>> > > +static void avr_xmega5_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPD); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPX); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPY); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > + avr_set_feature(env, AVR_FEATURE_RMW); >>> > > +} >>> > > + >>> > > +static void avr_xmega6_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > + avr_set_feature(env, AVR_FEATURE_RMW); >>> > > +} >>> > > + >>> > > +static void avr_xmega7_initfn(Object *obj) >>> > > +{ >>> > > + AVRCPU *cpu = AVR_CPU(obj); >>> > > + CPUAVRState *env = &cpu->env; >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_LPM); >>> > > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); >>> > > + avr_set_feature(env, AVR_FEATURE_SRAM); >>> > > + avr_set_feature(env, AVR_FEATURE_BREAK); >>> > > + >>> > > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); >>> > > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPD); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPX); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPY); >>> > > + avr_set_feature(env, AVR_FEATURE_RAMPZ); >>> > > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_ELPM); >>> > > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); >>> > > + avr_set_feature(env, AVR_FEATURE_LPMX); >>> > > + avr_set_feature(env, AVR_FEATURE_MOVW); >>> > > + avr_set_feature(env, AVR_FEATURE_MUL); >>> > > + avr_set_feature(env, AVR_FEATURE_RMW); >>> > > +} >>> > > + >>> > > +typedef struct AVRCPUInfo { >>> > > + const char *name; >>> > > + void (*initfn)(Object *obj); >>> > > +} AVRCPUInfo; >>> > > + >>> > > + >>> > > +static void avr_cpu_list_entry(gpointer data, gpointer user_data) >>> > > +{ >>> > > + const char *typename = object_class_get_name(OBJECT_ >>> CLASS(data)); >>> > > + >>> > > + qemu_printf("%s\n", typename); >>> > > +} >>> > > + >>> > > +void avr_cpu_list(void) >>> > > +{ >>> > > + GSList *list; >>> > > + list = object_class_get_list_sorted(TYPE_AVR_CPU, false); >>> > > + g_slist_foreach(list, avr_cpu_list_entry, NULL); >>> > > + g_slist_free(list); >>> > > +} >>> > > + >>> > > +#define DEFINE_AVR_CPU_TYPE(model, initfn) \ >>> > > + { \ >>> > > + .parent = TYPE_AVR_CPU, \ >>> > > + .instance_init = initfn, \ >>> > > + .name = model "-avr-cpu", \ >>> > > + } >>> > > + >>> > > +static const TypeInfo avr_cpu_type_info[] = { >>> > > + { >>> > > + .name = TYPE_AVR_CPU, >>> > > + .parent = TYPE_CPU, >>> > > + .instance_size = sizeof(AVRCPU), >>> > > + .instance_init = avr_cpu_initfn, >>> > > + .class_size = sizeof(AVRCPUClass), >>> > > + .class_init = avr_cpu_class_init, >>> > > + .abstract = true, >>> > > + }, >>> > > + DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6_initfn), >>> > > + DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7_initfn), >>> > > +}; >>> > > + >>> > >>> > Hi, Michael, >>> > >>> > I have the hardest time finding in the documentation some kind of >>> > table of AVR CPUs containing supported features. Related to that: >>> > >>> > - Is there a list in the docs equivalent to the definitions of >>> > AVR_FEATURE_XXX constants in your code? >>> > - How did you collect all info needed for definition of 15 CPUs above >>> > (link to the source of info would be great)? >>> > - Would all 15 CPUs be supported in QEMU once this series is >>> > integrated, without caveats? >>> > >>> > Sincerely yours, >>> > Aleksandar >>> >>> Hi Alexandar. >>> >>> you can find this info in different source >>> 1. this wiki https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set >> >> >> Hmm. Introducing a new target to QEMU based on Wikipedia article? >> >> >>> 2. download all the speck and compare >> >> >> It would be helpful if you provided links to the specs you meant here. >> >> >>> 3. GCC >>> 1. https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html >>> 2. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/ >>> avr/avr-mcus.def >>> 3. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/ >>> avr/avr-arch.h >>> 4. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/ >>> avr/avr-devices.c >>> >>> >> QEMU should not be dependent on gcc code, as it is, by its definition, a >> compiler-agnostic tool. Dependence on gcc opens the possibility of >> importing bugs from gcc, among other problems. >> >> It appears to me that all AVR_FEATURE_XXX constants are pure gcc >> constructs, never mentioned (unfortunately) in official AVR documentation, >> or some comparison table by the vendor. I understand that it is nice to >> have the same organuzation of such flags both in QEMU and gcc, but gcc is >> not QEMU's reference, and your checking each single item related to >> AVR_FEATURE_XXX in the AVR documentation would be much appreciated. I know >> it is a lot of work - but is there any other better solution than just >> copying the code from gcc? >> >> Thanks, Aleksandar >> >> >>> as for the flags >>> 1. AVR_FEATURE_SRAM defined but never used >>> 2. AVR_FEATURE_LPM assigned for all cores, however there are more >>> cores that do not support this instruction, so if added to QEMU will >>> not have it defined for them. >>> >>> >>> >>> -- >>> Best Regards, >>> Michael Rolnik >>> >> > > -- > Best Regards, > Michael Rolnik > --00000000000001a705059899dbcc Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Saturday, November 30, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
Aleksandar.

if download A= VR specs you can see that some cores implement some instructions and some d= on't.
We could go other way, just implement all of them regar= dless of what is supported and what is not and hope that executed elf conta= ins only supported ones.


The current way is much better than a single "super-core"= ;, absolutely. OK, sorry, it was quite unresonable from me to request from = you checking 400+ (or perhaps 500+) existing AVR microcontroller specificat= ions for all features (boy, these numbers are staggering). But, in future, = while extending or revising AVR support, please consider specification shee= ts as really the only valid reference.

Have a grea= t weekend!
Aleksandar


Regards,
<= div>Michael Rolnik



On Sat, Nov 30, 2019= at 6:22 PM Aleksandar Markovic <aleksandar.m.mail@gmail.com> wrote:


On Saturday, N= ovember 23, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
On Fri, Nov 22, 2019 at 7:12 PM Aleksandar Mark= ovic
<aleksa= ndar.m.mail@gmail.com> wrote:
>
> > +
> > +static void avr_avr1_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +}
> > +
> > +static void avr_avr2_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +}
> > +
> > +static void avr_avr25_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +}
> > +
> > +static void avr_avr3_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +}
> > +
> > +static void avr_avr31_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +}
> > +
> > +static void avr_avr35_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +}
> > +
> > +static void avr_avr4_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +}
> > +
> > +static void avr_avr5_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +}
> > +
> > +static void avr_avr51_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +}
> > +
> > +static void avr_avr6_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +}
> > +
> > +static void avr_xmega2_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
> > +}
> > +
> > +static void avr_xmega4_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
> > +}
> > +
> > +static void avr_xmega5_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPD);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPY);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
> > +}
> > +
> > +static void avr_xmega6_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
> > +}
> > +
> > +static void avr_xmega7_initfn(Object *obj)
> > +{
> > +=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
> > +=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
> > +
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPD);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPY);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
> > +=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
> > +}
> > +
> > +typedef struct AVRCPUInfo {
> > +=C2=A0 =C2=A0 const char *name;
> > +=C2=A0 =C2=A0 void (*initfn)(Object *obj);
> > +} AVRCPUInfo;
> > +
> > +
> > +static void avr_cpu_list_entry(gpointer data, gpointer user_data= )
> > +{
> > +=C2=A0 =C2=A0 const char *typename =3D object_class_get_name(OBJ= ECT_CLASS(data));
> > +
> > +=C2=A0 =C2=A0 qemu_printf("%s\n", typename);
> > +}
> > +
> > +void avr_cpu_list(void)
> > +{
> > +=C2=A0 =C2=A0 GSList *list;
> > +=C2=A0 =C2=A0 list =3D object_class_get_list_sorted(TYPE_AV= R_CPU, false);
> > +=C2=A0 =C2=A0 g_slist_foreach(list, avr_cpu_list_entry, NULL); > > +=C2=A0 =C2=A0 g_slist_free(list);
> > +}
> > +
> > +#define DEFINE_AVR_CPU_TYPE(model, initfn) \
> > +=C2=A0 =C2=A0 { \
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .parent =3D TYPE_AVR_CPU, \
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_init =3D initfn, \
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .name =3D model "-avr-cpu"= , \
> > +=C2=A0 =C2=A0 }
> > +
> > +static const TypeInfo avr_cpu_type_info[] =3D {
> > +=C2=A0 =C2=A0 {
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .name =3D TYPE_AVR_CPU,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .parent =3D TYPE_CPU,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_size =3D sizeof(AVRCPU), > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_init =3D avr_cpu_initfn, > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .class_size =3D sizeof(AVRCPUClass),=
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .class_init =3D avr_cpu_class_init,<= br> > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 .abstract =3D true,
> > +=C2=A0 =C2=A0 },
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_i= nitfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_i= nitfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_i= nitfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_i= nitfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_ini= tfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2= _initfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4= _initfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5= _initfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6= _initfn),
> > +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7= _initfn),
> > +};
> > +
>
> Hi, Michael,
>
> I have the hardest time finding in the documentation some kind of
> table of AVR CPUs containing supported features. Related to that:
>
> - Is there a list in the docs equivalent to the definitions of
> AVR_FEATURE_XXX constants in your code?
> - How did you collect all info needed for definition of 15 CPUs above<= br> > (link to the source of info would be great)?
> - Would all 15 CPUs be supported in QEMU once this series is
> integrated, without caveats?
>
> Sincerely yours,
> Aleksandar

Hi Alexandar.

you can find this info in different source
1. this wiki https://en.wikipedia.org/wiki/Atmel_AVR_instru= ction_set

Hmm. Introducing a new target= to QEMU based on Wikipedia article?
=C2=A0
2. download all the speck and compare

It wo= uld be helpful if you provided links to the specs you meant here.
=C2=A0
3. GCC
=C2=A0 =C2=A0 1. https://gcc.gnu.org/onlinedocs/gcc/AVR-Options= .html
=C2=A0 =C2=A0 2. https://github.com/gcc-mirror= /gcc/blob/master/gcc/config/avr/avr-mcus.def
=C2=A0 =C2=A0 3. https://github.com/gcc-mirror/<= wbr>gcc/blob/master/gcc/config/avr/avr-arch.h
=C2=A0 =C2=A0 4. https://github.com/gcc-mirro= r/gcc/blob/master/gcc/config/avr/avr-devices.c


QEMU should not be dependent on gcc co= de, as it is, by its definition, a compiler-agnostic tool. Dependence on gc= c opens the possibility of importing bugs from gcc, among other problems.

It appears to me that all AVR_FEATURE_XXX constants= are pure gcc constructs, never mentioned (unfortunately) in official AVR d= ocumentation, or some comparison table by the vendor. I understand that it = is nice to have the same organuzation of such flags both in QEMU and gcc, b= ut gcc is not QEMU's reference, and your checking each single item rela= ted to AVR_FEATURE_XXX=C2=A0in the AVR documentation would be much apprecia= ted. I know it is a lot of work - but is there any other better solution th= an just copying the code from gcc?

Thanks, Aleksan= dar
=C2=A0
as for the flags
1. AVR_FEATURE_SRAM defined but never used
2. AVR_FEATURE_LPM assigned for all cores, however there are more
cores that do not support this instruction, so if added to QEMU will
not have it defined for them.



--
Best Regards,
Michael Rolnik


--
Best Regards,
Michael Rolnik
--00000000000001a705059899dbcc--