* [PATCH v8 01/14] target/mips: msa: Split helpers for MADDV.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 02/14] target/mips: msa: Split helpers for MSUBV.<B|H|W|D> Aleksandar Markovic
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 19 ++++++++--
3 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 84fdd9fd27..e479a22559 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -950,6 +950,11 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -1069,7 +1074,6 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c3b271934a..3b75bdc6a4 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2883,7 +2883,77 @@ void helper_msa_mod_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Multiply group helpers here */
+static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ return dest + arg1 * arg2;
+}
+
+void helper_msa_maddv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_maddv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_maddv_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_maddv_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_maddv_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_maddv_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_maddv_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_maddv_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_maddv_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_maddv_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_maddv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_maddv_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_maddv_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_maddv_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_maddv_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_maddv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_maddv_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_maddv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
/*
@@ -4816,12 +4886,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- return dest + arg1 * arg2;
-}
-
static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5002,7 +5066,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(maddv)
MSA_TEROP_DF(msubv)
MSA_TEROP_DF(dpadd_s)
MSA_TEROP_DF(dpadd_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2caf4cba5a..0f33496962 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29057,6 +29057,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MADDV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_maddv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_maddv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_maddv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_maddv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_ASUB_S_df:
switch (df) {
case DF_BYTE:
@@ -29283,9 +29299,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBS_U_df:
gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADDV_df:
- gen_helper_msa_maddv_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SPLAT_df:
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 02/14] target/mips: msa: Split helpers for MSUBV.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 01/14] target/mips: msa: Split helpers for MADDV.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 03/14] target/mips: msa: Split helpers for DPADD_S.<H|W|D> Aleksandar Markovic
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 19 ++++++++--
3 files changed, 93 insertions(+), 11 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index e479a22559..7ca0036807 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -955,6 +955,11 @@ DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -1074,7 +1079,6 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 3b75bdc6a4..2b54de0959 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2955,6 +2955,78 @@ void helper_msa_maddv_d(CPUMIPSState *env,
pwd->d[1] = msa_maddv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
}
+static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ return dest - arg1 * arg2;
+}
+
+void helper_msa_msubv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_msubv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_msubv_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_msubv_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_msubv_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_msubv_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_msubv_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_msubv_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_msubv_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_msubv_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_msubv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_msubv_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_msubv_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_msubv_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_msubv_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_msubv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_msubv_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_msubv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
+
/*
* Int Subtract
@@ -4886,12 +4958,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- return dest - arg1 * arg2;
-}
-
static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5066,7 +5132,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(msubv)
MSA_TEROP_DF(dpadd_s)
MSA_TEROP_DF(dpadd_u)
MSA_TEROP_DF(dpsub_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0f33496962..a5e16e855c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29073,6 +29073,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MSUBV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_msubv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_msubv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_msubv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_msubv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_ASUB_S_df:
switch (df) {
case DF_BYTE:
@@ -29305,9 +29321,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBSUS_U_df:
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUBV_df:
- gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 03/14] target/mips: msa: Split helpers for DPADD_S.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 01/14] target/mips: msa: Split helpers for MADDV.<B|H|W|D> Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 02/14] target/mips: msa: Split helpers for MSUBV.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 04/14] target/mips: msa: Split helpers for DPADD_U.<H|W|D> Aleksandar Markovic
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 4 +-
target/mips/msa_helper.c | 90 ++++++++++++++++++++++++++++------------
target/mips/translate.c | 12 +++++-
3 files changed, 78 insertions(+), 28 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 7ca0036807..16f2d53ad0 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1081,7 +1081,9 @@ DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
DEF_HELPER_5(msa_dpadd_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 2b54de0959..086b56f58c 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2224,7 +2224,70 @@ void helper_msa_div_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Dot Product group helpers here */
+#define SIGNED_EXTRACT(e, o, a, df) \
+ do { \
+ e = SIGNED_EVEN(a, df); \
+ o = SIGNED_ODD(a, df); \
+ } while (0)
+
+#define UNSIGNED_EXTRACT(e, o, a, df) \
+ do { \
+ e = UNSIGNED_EVEN(a, df); \
+ o = UNSIGNED_ODD(a, df); \
+ } while (0)
+
+static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
+}
+
+void helper_msa_dpadd_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dpadd_s_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dpadd_s_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dpadd_s_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dpadd_s_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dpadd_s_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dpadd_s_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dpadd_s_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dpadd_s_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dpadd_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dpadd_s_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dpadd_s_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dpadd_s_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dpadd_s_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dpadd_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dpadd_s_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dpadd_s_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
/*
@@ -4785,18 +4848,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
return arg1 * arg2;
}
-#define SIGNED_EXTRACT(e, o, a, df) \
- do { \
- e = SIGNED_EVEN(a, df); \
- o = SIGNED_ODD(a, df); \
- } while (0)
-
-#define UNSIGNED_EXTRACT(e, o, a, df) \
- do { \
- e = UNSIGNED_EVEN(a, df); \
- o = UNSIGNED_ODD(a, df); \
- } while (0)
-
static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t even_arg1;
@@ -4958,18 +5009,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
-}
-
static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5132,7 +5171,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(dpadd_s)
MSA_TEROP_DF(dpadd_u)
MSA_TEROP_DF(dpsub_s)
MSA_TEROP_DF(dpsub_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a5e16e855c..94c3d15f2d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29399,7 +29399,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_DPADD_S_df:
- gen_helper_msa_dpadd_s_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DPADD_U_df:
gen_helper_msa_dpadd_u_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 04/14] target/mips: msa: Split helpers for DPADD_U.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (2 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 03/14] target/mips: msa: Split helpers for DPADD_S.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 05/14] target/mips: msa: Split helpers for DPSUB_S.<H|W|D> Aleksandar Markovic
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67 ++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 12 ++++++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 16f2d53ad0..155b6bbe3e 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1084,7 +1084,9 @@ DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_dpadd_u_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 086b56f58c..9741c94d27 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2290,6 +2290,60 @@ void helper_msa_dpadd_s_d(CPUMIPSState *env,
}
+static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
+}
+
+void helper_msa_dpadd_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dpadd_u_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dpadd_u_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dpadd_u_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dpadd_u_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dpadd_u_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dpadd_u_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dpadd_u_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dpadd_u_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dpadd_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dpadd_u_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dpadd_u_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dpadd_u_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dpadd_u_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dpadd_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dpadd_u_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dpadd_u_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Max Min
* -----------
@@ -5009,18 +5063,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
-}
-
static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5171,7 +5213,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(dpadd_u)
MSA_TEROP_DF(dpsub_s)
MSA_TEROP_DF(dpsub_u)
MSA_TEROP_DF(binsl)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 94c3d15f2d..009ac5c1fb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29412,7 +29412,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DPADD_U_df:
- gen_helper_msa_dpadd_u_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DPSUB_S_df:
gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 05/14] target/mips: msa: Split helpers for DPSUB_S.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (3 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 04/14] target/mips: msa: Split helpers for DPADD_U.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 06/14] target/mips: msa: Split helpers for DPSUB_U.<H|W|D> Aleksandar Markovic
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67 ++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 12 ++++++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 155b6bbe3e..2de14542cd 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1087,7 +1087,9 @@ DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 9741c94d27..934f705c1e 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2344,6 +2344,60 @@ void helper_msa_dpadd_u_d(CPUMIPSState *env,
}
+static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
+}
+
+void helper_msa_dpsub_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dpsub_s_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dpsub_s_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dpsub_s_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dpsub_s_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dpsub_s_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dpsub_s_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dpsub_s_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dpsub_s_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dpsub_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dpsub_s_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dpsub_s_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dpsub_s_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dpsub_s_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dpsub_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dpsub_s_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dpsub_s_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Max Min
* -----------
@@ -5063,18 +5117,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
-}
-
static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5213,7 +5255,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(dpsub_s)
MSA_TEROP_DF(dpsub_u)
MSA_TEROP_DF(binsl)
MSA_TEROP_DF(binsr)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 009ac5c1fb..2576905e5b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29425,7 +29425,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DPSUB_S_df:
- gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DPSUB_U_df:
gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 06/14] target/mips: msa: Split helpers for DPSUB_U.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (4 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 05/14] target/mips: msa: Split helpers for DPSUB_S.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 07/14] target/mips: msa: Split helpers for DOTP_S.<H|W|D> Aleksandar Markovic
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 67 ++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 12 ++++++-
3 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 2de14542cd..575f4a524c 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1090,7 +1090,9 @@ DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 934f705c1e..33d5251a6b 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2398,6 +2398,60 @@ void helper_msa_dpsub_s_d(CPUMIPSState *env,
}
+static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
+ int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
+}
+
+void helper_msa_dpsub_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dpsub_u_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dpsub_u_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dpsub_u_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dpsub_u_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dpsub_u_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dpsub_u_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dpsub_u_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dpsub_u_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dpsub_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dpsub_u_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dpsub_u_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dpsub_u_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dpsub_u_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dpsub_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dpsub_u_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dpsub_u_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Max Min
* -----------
@@ -5117,18 +5171,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
}
-static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
-}
-
static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5255,7 +5297,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
} \
}
-MSA_TEROP_DF(dpsub_u)
MSA_TEROP_DF(binsl)
MSA_TEROP_DF(binsr)
MSA_TEROP_DF(madd_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2576905e5b..3dda242643 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29438,7 +29438,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DPSUB_U_df:
- gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
}
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 07/14] target/mips: msa: Split helpers for DOTP_S.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (5 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 06/14] target/mips: msa: Split helpers for DPSUB_U.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 08/14] target/mips: msa: Split helpers for DOTP_U.<H|W|D> Aleksandar Markovic
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 5 ++-
target/mips/msa_helper.c | 66 ++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 12 +++++++-
3 files changed, 69 insertions(+), 14 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 575f4a524c..06df3de744 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1079,7 +1079,10 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 33d5251a6b..201283fdd9 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2236,6 +2236,60 @@ void helper_msa_div_u_d(CPUMIPSState *env,
o = UNSIGNED_ODD(a, df); \
} while (0)
+
+static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
+}
+
+void helper_msa_dotp_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dotp_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dotp_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dotp_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dotp_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dotp_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dotp_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dotp_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dotp_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dotp_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dotp_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dotp_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dotp_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dotp_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dotp_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dotp_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dotp_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5010,17 +5064,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
return arg1 * arg2;
}
-static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
-}
-
static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t even_arg1;
@@ -5155,7 +5198,6 @@ MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
MSA_BINOP_DF(mulv)
-MSA_BINOP_DF(dotp_s)
MSA_BINOP_DF(dotp_u)
MSA_BINOP_DF(mul_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3dda242643..f0bab46378 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29393,7 +29393,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DOTP_S_df:
- gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DOTP_U_df:
gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 08/14] target/mips: msa: Split helpers for DOTP_U.<H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (6 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 07/14] target/mips: msa: Split helpers for DOTP_S.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 09/14] target/mips: msa: Split helpers for SUBS_S.<B|H|W|D> Aleksandar Markovic
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 4 ++-
target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 12 +++++++-
3 files changed, 67 insertions(+), 14 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 06df3de744..05d5533dfb 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -1083,7 +1083,9 @@ DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 201283fdd9..84d0073918 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2290,6 +2290,59 @@ void helper_msa_dotp_s_d(CPUMIPSState *env,
}
+static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int64_t even_arg1;
+ int64_t even_arg2;
+ int64_t odd_arg1;
+ int64_t odd_arg2;
+ UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
+ UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
+ return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
+}
+
+void helper_msa_dotp_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_dotp_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_dotp_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_dotp_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_dotp_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_dotp_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_dotp_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_dotp_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_dotp_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_dotp_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_dotp_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_dotp_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_dotp_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_dotp_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_dotp_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_dotp_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_dotp_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
@@ -5064,17 +5117,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
return arg1 * arg2;
}
-static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int64_t even_arg1;
- int64_t even_arg2;
- int64_t odd_arg1;
- int64_t odd_arg2;
- UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
- UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
- return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
-}
-
#define CONCATENATE_AND_SLIDE(s, k) \
do { \
for (i = 0; i < s; i++) { \
@@ -5198,7 +5240,6 @@ MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
MSA_BINOP_DF(mulv)
-MSA_BINOP_DF(dotp_u)
MSA_BINOP_DF(mul_q)
MSA_BINOP_DF(mulr_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f0bab46378..b56bdf54af 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29406,7 +29406,17 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DOTP_U_df:
- gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DPADD_S_df:
switch (df) {
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 09/14] target/mips: msa: Split helpers for SUBS_S.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (7 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 08/14] target/mips: msa: Split helpers for DOTP_U.<H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 10/14] target/mips: msa: Split helpers for SUBS_U.<B|H|W|D> Aleksandar Markovic
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 90 ++++++++++++++++++++++++++++++++++------
target/mips/translate.c | 15 ++++++-
3 files changed, 97 insertions(+), 14 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 05d5533dfb..a93402a2d3 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -978,6 +978,11 @@ DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1074,7 +1079,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 84d0073918..f08beba123 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3650,6 +3650,84 @@ void helper_msa_hsub_u_d(CPUMIPSState *env,
}
+static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int64_t max_int = DF_MAX_INT(df);
+ int64_t min_int = DF_MIN_INT(df);
+ if (arg2 > 0) {
+ return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
+ } else {
+ return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
+ }
+}
+
+void helper_msa_subs_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_subs_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_subs_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_subs_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_subs_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_subs_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_subs_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_subs_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_subs_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_subs_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_subs_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_subs_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_subs_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_subs_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_subs_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_subs_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_subs_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_subs_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_subs_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_subs_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_subs_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_subs_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_subs_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_subs_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_subs_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_subs_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_subs_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_subs_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_subs_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_subs_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_subs_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_subs_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_subs_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_subs_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Interleave
* ----------
@@ -5060,17 +5138,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int64_t max_int = DF_MAX_INT(df);
- int64_t min_int = DF_MIN_INT(df);
- if (arg2 > 0) {
- return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
- } else {
- return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
- }
-}
-
static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
@@ -5235,7 +5302,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
}
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(subs_s)
MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b56bdf54af..7b54d60f70 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29298,7 +29298,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_SUBS_S_df:
- gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_MULV_df:
gen_helper_msa_mulv_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 10/14] target/mips: msa: Split helpers for SUBS_U.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (8 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 09/14] target/mips: msa: Split helpers for SUBS_S.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 11/14] target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D> Aleksandar Markovic
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 82 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 15 +++++++-
3 files changed, 93 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index a93402a2d3..61dc1ed626 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -983,6 +983,11 @@ DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1079,7 +1084,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f08beba123..bce32abf77 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3728,6 +3728,80 @@ void helper_msa_subs_s_d(CPUMIPSState *env,
}
+static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
+}
+
+void helper_msa_subs_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_subs_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_subs_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_subs_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_subs_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_subs_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_subs_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_subs_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_subs_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_subs_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_subs_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_subs_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_subs_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_subs_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_subs_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_subs_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_subs_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_subs_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_subs_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_subs_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_subs_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_subs_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_subs_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_subs_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_subs_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_subs_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_subs_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_subs_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_subs_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_subs_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_subs_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_subs_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_subs_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_subs_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Interleave
* ----------
@@ -5138,13 +5212,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
-}
-
static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
@@ -5302,7 +5369,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
}
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
MSA_BINOP_DF(mulv)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7b54d60f70..cdf5e939de 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29326,7 +29326,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBS_U_df:
- gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_SPLAT_df:
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 11/14] target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (9 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 10/14] target/mips: msa: Split helpers for SUBS_U.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 12/14] target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D> Aleksandar Markovic
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 102 ++++++++++++++++++++++++++++++++-------
target/mips/translate.c | 15 +++++-
3 files changed, 103 insertions(+), 20 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 61dc1ed626..227ff76ec1 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -988,6 +988,11 @@ DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1084,7 +1089,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index bce32abf77..f7e5c018ac 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3802,6 +3802,90 @@ void helper_msa_subs_u_d(CPUMIPSState *env,
}
+static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t max_uint = DF_MAX_UINT(df);
+ if (arg2 >= 0) {
+ uint64_t u_arg2 = (uint64_t)arg2;
+ return (u_arg1 > u_arg2) ?
+ (int64_t)(u_arg1 - u_arg2) :
+ 0;
+ } else {
+ uint64_t u_arg2 = (uint64_t)(-arg2);
+ return (u_arg1 < max_uint - u_arg2) ?
+ (int64_t)(u_arg1 + u_arg2) :
+ (int64_t)max_uint;
+ }
+}
+
+void helper_msa_subsus_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_subsus_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_subsus_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_subsus_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_subsus_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_subsus_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_subsus_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_subsus_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_subsus_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_subsus_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_subsus_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_subsus_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_subsus_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_subsus_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_subsus_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_subsus_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_subsus_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_subsus_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_subsus_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_subsus_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_subsus_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_subsus_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_subsus_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_subsus_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_subsus_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_subsus_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_subsus_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_subsus_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_subsus_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_subsus_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_subsus_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_subsus_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_subsus_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_subsus_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Interleave
* ----------
@@ -5212,23 +5296,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t max_uint = DF_MAX_UINT(df);
- if (arg2 >= 0) {
- uint64_t u_arg2 = (uint64_t)arg2;
- return (u_arg1 > u_arg2) ?
- (int64_t)(u_arg1 - u_arg2) :
- 0;
- } else {
- uint64_t u_arg2 = (uint64_t)(-arg2);
- return (u_arg1 < max_uint - u_arg2) ?
- (int64_t)(u_arg1 + u_arg2) :
- (int64_t)max_uint;
- }
-}
-
static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
@@ -5369,7 +5436,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
}
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
MSA_BINOP_DF(mulv)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cdf5e939de..1a95fe08fc 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29345,7 +29345,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBSUS_U_df:
- gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 12/14] target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (10 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 11/14] target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 13/14] target/mips: msa: Split helpers for SUBV.<B|H|W|D> Aleksandar Markovic
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 102 ++++++++++++++++++++++++++++++++-------
target/mips/translate.c | 15 +++++-
3 files changed, 103 insertions(+), 20 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 227ff76ec1..4795c97f47 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -993,6 +993,11 @@ DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1089,7 +1094,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f7e5c018ac..27a9c36a89 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3886,6 +3886,90 @@ void helper_msa_subsus_u_d(CPUMIPSState *env,
}
+static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ int64_t max_int = DF_MAX_INT(df);
+ int64_t min_int = DF_MIN_INT(df);
+ if (u_arg1 > u_arg2) {
+ return u_arg1 - u_arg2 < (uint64_t)max_int ?
+ (int64_t)(u_arg1 - u_arg2) :
+ max_int;
+ } else {
+ return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
+ (int64_t)(u_arg1 - u_arg2) :
+ min_int;
+ }
+}
+
+void helper_msa_subsuu_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_subsuu_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_subsuu_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_subsuu_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_subsuu_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_subsuu_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_subsuu_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_subsuu_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_subsuu_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_subsuu_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_subsuu_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_subsuu_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_subsuu_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_subsuu_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_subsuu_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_subsuu_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_subsuu_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_subsuu_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_subsuu_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_subsuu_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_subsuu_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_subsuu_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_subsuu_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_subsuu_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_subsuu_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_subsuu_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_subsuu_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_subsuu_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_subsuu_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_subsuu_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_subsuu_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_subsuu_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_subsuu_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_subsuu_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Interleave
* ----------
@@ -5296,23 +5380,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- int64_t max_int = DF_MAX_INT(df);
- int64_t min_int = DF_MIN_INT(df);
- if (u_arg1 > u_arg2) {
- return u_arg1 - u_arg2 < (uint64_t)max_int ?
- (int64_t)(u_arg1 - u_arg2) :
- max_int;
- } else {
- return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
- (int64_t)(u_arg1 - u_arg2) :
- min_int;
- }
-}
-
static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 * arg2;
@@ -5436,7 +5503,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
}
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(subsuu_s)
MSA_BINOP_DF(mulv)
MSA_BINOP_DF(mul_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1a95fe08fc..3509613798 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29361,7 +29361,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_SUBSUU_S_df:
- gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_DOTP_S_df:
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 13/14] target/mips: msa: Split helpers for SUBV.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (11 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 12/14] target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-13 15:21 ` [PATCH v8 14/14] target/mips: msa: Split helpers for MULV.<B|H|W|D> Aleksandar Markovic
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 81 +++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 15 +++++++-
3 files changed, 91 insertions(+), 11 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 4795c97f47..5d7ba6a847 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -998,6 +998,11 @@ DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1093,7 +1098,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 27a9c36a89..d099e00b40 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3553,9 +3553,6 @@ void helper_msa_asub_u_d(CPUMIPSState *env,
}
-/* TODO: insert the rest of Int Subtract group helpers here */
-
-
static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
@@ -3970,6 +3967,78 @@ void helper_msa_subsuu_s_d(CPUMIPSState *env,
}
+static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return arg1 - arg2;
+}
+
+void helper_msa_subv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_subv_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_subv_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_subv_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_subv_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_subv_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_subv_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_subv_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_subv_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_subv_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_subv_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_subv_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_subv_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_subv_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_subv_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_subv_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_subv_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_subv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_subv_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_subv_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_subv_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_subv_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_subv_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_subv_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_subv_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_subv_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_subv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_subv_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_subv_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_subv_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_subv_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_subv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_subv_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_subv_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Interleave
* ----------
@@ -5194,11 +5263,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
-static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return arg1 - arg2;
-}
-
#define MSA_BINOP_IMM_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
uint32_t wd, uint32_t ws, int32_t u5) \
@@ -5502,7 +5566,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
} \
}
-MSA_BINOP_DF(subv)
MSA_BINOP_DF(mulv)
MSA_BINOP_DF(mul_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3509613798..6a6df58d29 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29323,7 +29323,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_SUBV_df:
- gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_subv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_subv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_subv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_subv_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_SUBS_U_df:
switch (df) {
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v8 14/14] target/mips: msa: Split helpers for MULV.<B|H|W|D>
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (12 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 13/14] target/mips: msa: Split helpers for SUBV.<B|H|W|D> Aleksandar Markovic
@ 2020-06-13 15:21 ` Aleksandar Markovic
2020-06-15 10:16 ` [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Rikalo
2020-06-15 19:14 ` Aleksandar Markovic
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-13 15:21 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
---
target/mips/helper.h | 6 ++-
target/mips/msa_helper.c | 79 ++++++++++++++++++++++++++++++++++++----
target/mips/translate.c | 15 +++++++-
3 files changed, 91 insertions(+), 9 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 5d7ba6a847..e97655dc0e 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -960,6 +960,11 @@ DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
@@ -1098,7 +1103,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index d099e00b40..6865addaf6 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3360,6 +3360,78 @@ void helper_msa_msubv_d(CPUMIPSState *env,
}
+static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return arg1 * arg2;
+}
+
+void helper_msa_mulv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_mulv_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_mulv_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_mulv_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_mulv_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_mulv_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_mulv_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_mulv_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_mulv_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_mulv_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_mulv_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_mulv_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_mulv_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_mulv_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_mulv_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_mulv_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_mulv_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_mulv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_mulv_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_mulv_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_mulv_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_mulv_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_mulv_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_mulv_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_mulv_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_mulv_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_mulv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_mulv_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_mulv_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_mulv_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_mulv_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_mulv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_mulv_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_mulv_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Subtract
* ------------
@@ -5444,11 +5516,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return arg1 * arg2;
-}
-
#define CONCATENATE_AND_SLIDE(s, k) \
do { \
for (i = 0; i < s; i++) { \
@@ -5566,8 +5633,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
} \
}
-MSA_BINOP_DF(mulv)
-
MSA_BINOP_DF(mul_q)
MSA_BINOP_DF(mulr_q)
#undef MSA_BINOP_DF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a6df58d29..8fe79cc4ca 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29314,7 +29314,20 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_MULV_df:
- gen_helper_msa_mulv_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_mulv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_mulv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_mulv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_mulv_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_SLD_df:
gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (13 preceding siblings ...)
2020-06-13 15:21 ` [PATCH v8 14/14] target/mips: msa: Split helpers for MULV.<B|H|W|D> Aleksandar Markovic
@ 2020-06-15 10:16 ` Aleksandar Rikalo
2020-06-15 19:14 ` Aleksandar Markovic
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Rikalo @ 2020-06-15 10:16 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
> This series contains some patches that split heprers in msa_helper.c.
> It will make easier for debugging tools to display involved source
> code, and also introduces some modest performance improvements gains
> for all involved MSA instructions.
>
> v7->v8:
>
> - added six new demacroing patches
>
> v6->v7:
>
> - excluded patches that have been already upstreamed
> - added six new demacroing patches
>
> v5->v6:
>
> - excluded a patch that was included by mistake
>
> v4->v5:
>
> - corrected some spelling and style mistakes in commit messages
> - added changing MAINTAINERS too while renaming files
> - added two patches on splitting helpers in msa_helper.c
>
> v3->v4:
>
> - corrected some spelling and style mistakes in commit messages
> - added a patch on renaming some files in hw/mips
>
> v2->v3:
>
> - changed Malta patch to perform logging
> - added change of Aleksandar Rikalo's email
>
> v1->v2:
>
> - added more demacroing
>
> Aleksandar Markovic (14):
> target/mips: msa: Split helpers for MADDV.<B|H|W|D>
> target/mips: msa: Split helpers for MSUBV.<B|H|W|D>
> target/mips: msa: Split helpers for DPADD_S.<H|W|D>
> target/mips: msa: Split helpers for DPADD_U.<H|W|D>
> target/mips: msa: Split helpers for DPSUB_S.<H|W|D>
> target/mips: msa: Split helpers for DPSUB_U.<H|W|D>
> target/mips: msa: Split helpers for DOTP_S.<H|W|D>
> target/mips: msa: Split helpers for DOTP_U.<H|W|D>
> target/mips: msa: Split helpers for SUBS_S.<B|H|W|D>
> target/mips: msa: Split helpers for SUBS_U.<B|H|W|D>
> target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D>
> target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D>
> target/mips: msa: Split helpers for SUBV.<B|H|W|D>
> target/mips: msa: Split helpers for MULV.<B|H|W|D>
>
> target/mips/helper.h | 73 ++-
> target/mips/msa_helper.c | 1296 ++++++++++++++++++++++++++++++--------
> target/mips/translate.c | 200 +++++-
> 3 files changed, 1271 insertions(+), 298 deletions(-)
>
For the whole series:
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Please run all regression tests. Thank you.
Aleksandar Rikalo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements
2020-06-13 15:21 [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Markovic
` (14 preceding siblings ...)
2020-06-15 10:16 ` [PATCH v8 00/14] target/mips: MSA, FPU and other cleanups and improvements Aleksandar Rikalo
@ 2020-06-15 19:14 ` Aleksandar Markovic
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2020-06-15 19:14 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: aleksandar.rikalo, QEMU Developers
On Sat, Jun 13, 2020 at 5:22 PM Aleksandar Markovic
<aleksandar.qemu.devel@gmail.com> wrote:
>
> This series contains some patches that split heprers in msa_helper.c.
> It will make easier for debugging tools to display involved source
> code, and also introduces some modest performance improvements gains
> for all involved MSA instructions.
>
Applied to MIPS+misc queue.
> v7->v8:
>
> - added six new demacroing patches
>
> v6->v7:
>
> - excluded patches that have been already upstreamed
> - added six new demacroing patches
>
> v5->v6:
>
> - excluded a patch that was included by mistake
>
> v4->v5:
>
> - corrected some spelling and style mistakes in commit messages
> - added changing MAINTAINERS too while renaming files
> - added two patches on splitting helpers in msa_helper.c
>
> v3->v4:
>
> - corrected some spelling and style mistakes in commit messages
> - added a patch on renaming some files in hw/mips
>
> v2->v3:
>
> - changed Malta patch to perform logging
> - added change of Aleksandar Rikalo's email
>
> v1->v2:
>
> - added more demacroing
>
> Aleksandar Markovic (14):
> target/mips: msa: Split helpers for MADDV.<B|H|W|D>
> target/mips: msa: Split helpers for MSUBV.<B|H|W|D>
> target/mips: msa: Split helpers for DPADD_S.<H|W|D>
> target/mips: msa: Split helpers for DPADD_U.<H|W|D>
> target/mips: msa: Split helpers for DPSUB_S.<H|W|D>
> target/mips: msa: Split helpers for DPSUB_U.<H|W|D>
> target/mips: msa: Split helpers for DOTP_S.<H|W|D>
> target/mips: msa: Split helpers for DOTP_U.<H|W|D>
> target/mips: msa: Split helpers for SUBS_S.<B|H|W|D>
> target/mips: msa: Split helpers for SUBS_U.<B|H|W|D>
> target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D>
> target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D>
> target/mips: msa: Split helpers for SUBV.<B|H|W|D>
> target/mips: msa: Split helpers for MULV.<B|H|W|D>
>
> target/mips/helper.h | 73 ++-
> target/mips/msa_helper.c | 1296 ++++++++++++++++++++++++++++++--------
> target/mips/translate.c | 200 +++++-
> 3 files changed, 1271 insertions(+), 298 deletions(-)
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread