From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AAD6CA9EAF for ; Sun, 27 Oct 2019 07:45:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2191C20717 for ; Sun, 27 Oct 2019 07:45:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OHeMeX2K" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2191C20717 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iOdEc-00034b-9l for qemu-devel@archiver.kernel.org; Sun, 27 Oct 2019 03:45:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36994) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iOdDo-0001xZ-8h for qemu-devel@nongnu.org; Sun, 27 Oct 2019 03:44:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iOdDk-0003db-Qf for qemu-devel@nongnu.org; Sun, 27 Oct 2019 03:44:20 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]:38019) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iOdDk-0003dO-He for qemu-devel@nongnu.org; Sun, 27 Oct 2019 03:44:16 -0400 Received: by mail-ot1-x329.google.com with SMTP id r14so43059otn.5 for ; Sun, 27 Oct 2019 00:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=YOKuiXdfPO3KK/txzpZ/LHVNC8on230B40nga34VpW4=; b=OHeMeX2KMoJ+RqLr2nryXUV4lna1v/SISAEWu6MUvZtfkbzl5krRthanDSklG9Vljj IuMpptEpINoSYQTuTyfnQY6BfbpdvMVfC3joMWZStNfXmyKHmecK5wnHwd2utdRH71aV JGsLuAhO1VcQnZ2OinxSrOWbriEiXCpe3NGaTDrBqAqRF3TuA16KZaIsrdlZ3Dqncqe+ m012t2GB0uRagm/J+Ml3LMZmLWq9PSPaJbGJbT/CN7t35r7W4lL2E51qUgVsO3LnnU4A hAewwhJ/JVhfSMBo7v1iAvQExUxa5u69TUwZ7ojqo4G0wmrdn4UnYwin08dHM8YSEgbj VARg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=YOKuiXdfPO3KK/txzpZ/LHVNC8on230B40nga34VpW4=; b=hktgYpP3TXUw4Py/bWjwlnvtJ9FJMiIGSVoonv4kj8zOh9I5GBqOPXceD0QpjjJphY d/j6u+J6w6CV27jzMSX5ACuNAxEII+rRJyfagsxWoGRZ44AeROyBdbQD9fBULOkemyiR INy9JRMLzKmJ/+puC48o7vdWPtybegH+sgb5iTDC05RbOmlT0gNHYAbuLL0piqaJ7fmp gEqHTfF4fc9XJi/pYNYJBqZIWGrt+wogbdQ/cuPVw2ZltWPZb5hrzf5kdSLo+KuOFlRD n04tp7K7hDTkK/fbX1O3YiskEqeT/gmglQ7eSQLgV5E08XzliNuEA4u5aiOZsqHw4DpX OxvQ== X-Gm-Message-State: APjAAAW9pJTZTYoAeEbfNNGl/+5o7cHKbcIwqshc3UVdqn7uYArMrcjn 5SyI1cQmTcPntDDWetTpZyAfzen18xUFElmWczM= X-Google-Smtp-Source: APXvYqzXS3djOEZPvpKIoo/YFqcqo1HnoMHVgN1zwBZLu3UwCLet/xiamRKgH+nQEN9RcIqrdAL3jF7oFoEcnpF18rQ= X-Received: by 2002:a9d:4f0f:: with SMTP id d15mr3435887otl.64.1572162255112; Sun, 27 Oct 2019 00:44:15 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:340a:0:0:0:0:0 with HTTP; Sun, 27 Oct 2019 00:44:14 -0700 (PDT) In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> From: Aleksandar Markovic Date: Sun, 27 Oct 2019 08:44:14 +0100 Message-ID: Subject: Re: [PATCH v3 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000becf960595df8c56" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , "Michael S. Tsirkin" , "qemu-devel@nongnu.org" , Paolo Bonzini , =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Aleksandar Markovic , Igor Mammedov , Anthony Perard , "xen-devel@lists.xenproject.org" , Aleksandar Rikalo , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000becf960595df8c56 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Saturday, October 26, 2019, Philippe Mathieu-Daud=C3=A9 wrote: > Changes since v2 [0]: > - Use a #define > - Reword one description > - Added review tags (thanks all for reviewing!) > > Changes since v1 [1]: > - Removed patch reintroducing DO_UPCAST() use (thuth) > - Took various patches out to reduce series (thuth) > - Added review tags (thanks all for reviewing!) > > $ git backport-diff -u pc_split_i440fx_piix-v2 > Key: > [----] : patches are identical > [####] : number of functional differences between upstream/downstream pat= ch > [down] : patch is downstream-only > The flags [FC] indicate (F)unctional and (C)ontextual differences, > respectively > > 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC > Chipsets' > 002/20:[0004] [FC] 'piix4: Add the Reset Control Register' > 003/20:[0002] [FC] 'piix4: Add an i8259 Interrupt Controller as specified > in datasheet' > 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"' > 005/20:[----] [--] 'piix4: Rename PIIX4 object to piix4-isa' > 006/20:[----] [--] 'piix4: Add an i8257 DMA Controller as specified in > datasheet' > 007/20:[----] [-C] 'piix4: Add an i8254 PIT Controller as specified in > datasheet' > 008/20:[0004] [FC] 'piix4: Add a MC146818 RTC Controller as specified in > datasheet' > 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array > dynamically' > 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code a= s > piix4_create()' > 011/20:[----] [-C] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c' > 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state= _old > handlers' > 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()' > 014/20:[0002] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition= ' > 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route > Control Registers' > 016/20:[----] [-C] 'hw/pci-host/piix: Move i440FX declarations to > hw/pci-host/i440fx.h' > 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues' > 018/20:[----] [--] 'hw/pci-host/piix: Extract PIIX3 functions to > hw/isa/piix3.c' > 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as > 'i440fx'' > 020/20:[0004] [FC] 'hw/pci-host/i440fx: Remove the last PIIX3 traces' > > Previous cover: > > This series is a rework of "piix4: cleanup and improvements" [2] > from Herv=C3=A9, and my "remove i386/pc dependency: PIIX cleanup" [3]. > > Still trying to remove the strong X86/PC dependency 2 years later, > one step at a time. > Here we split the PIIX3 southbridge from i440FX northbridge. > The i440FX northbridge is only used by the PC machine, while the > PIIX southbridge is also used by the Malta MIPS machine. > > This is also a step forward using KConfig with the Malta board. > Without this split, it was impossible to compile the Malta without > pulling various X86 pieces of code. > > The overall design cleanup is not yet perfect, but enough to post > as a series. > > Now that the PIIX3 code is extracted, the code duplication with the > PIIX4 chipset is obvious. Not worth improving for now because it > isn't broken. > > Based-on: <1572097538-18898-1-git-send-email-pbonzini@redhat.com> > to include: > mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of > rtc_init() > https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com > > Since Aleksandar offered me to send the pull request [4] I plan to do > it once Paolo's pull [5] is merged. > > Philippe, I attempted the other day the integration of v2 of this series into MIPS pull request, but couldn't do it - since another series of yours was already merged, acting on the same code, making rebasing difficult. Now this, v3, series can't be applied since certain patches in some, on surface, unrelated series aren't megred, and v3 assumes they are merged. If you send a series, it should preferably be based on the latest (current) code base, not on some imagined future state. Why did you create this such mess with interdependencies of your own multiple series, and just right before softfreeze? :( You should have distributed submitting those series over longer time interval, and absolutely avoid, if possible, this hectic around-softfreeze period. You did the opposite: waited for softfreeze to become close, and sent several interdependant series in matter of days - creating stress without any real technical reason. In case you, for any reason, can't complete this by softfreeze, I advice you not to rush, and postpone the integration to 5.0. Thanks, Aleksandar > Thanks, > > Phil. > > CI results: > https://travis-ci.org/philmd/qemu/builds/603253987 > https://app.shippable.com/github/philmd/qemu/runs/550/summary/console > > [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg04662.html > [1] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html > [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html > [3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html > [4] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg04959.html > [5] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg07339.html > > Herv=C3=A9 Poussineau (5): > piix4: Add the Reset Control Register > piix4: Add an i8259 Interrupt Controller as specified in datasheet > piix4: Rename PIIX4 object to piix4-isa > piix4: Add an i8257 DMA Controller as specified in datasheet > piix4: Add an i8254 PIT Controller as specified in datasheet > > Philippe Mathieu-Daud=C3=A9 (15): > MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets > Revert "irq: introduce qemu_irq_proxy()" > piix4: Add a MC146818 RTC Controller as specified in datasheet > hw/mips/mips_malta: Create IDE hard drive array dynamically > hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() > hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c > hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers > hw/pci-host/piix: Extract piix3_create() > hw/pci-host/piix: Move RCR_IOPORT register definition > hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers > hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h > hw/pci-host/piix: Fix code style issues > hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c > hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' > hw/pci-host/i440fx: Remove the last PIIX3 traces > > MAINTAINERS | 14 +- > hw/acpi/pcihp.c | 2 +- > hw/acpi/piix4.c | 42 +-- > hw/core/irq.c | 14 - > hw/i386/Kconfig | 3 +- > hw/i386/acpi-build.c | 5 +- > hw/i386/pc_piix.c | 10 +- > hw/i386/xen/xen-hvm.c | 5 +- > hw/intc/apic_common.c | 49 ---- > hw/isa/Kconfig | 4 + > hw/isa/Makefile.objs | 1 + > hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++ > hw/isa/piix4.c | 151 ++++++++++- > hw/mips/gt64xxx_pci.c | 5 +- > hw/mips/mips_malta.c | 46 +--- > hw/pci-host/Kconfig | 3 +- > hw/pci-host/Makefile.objs | 2 +- > hw/pci-host/{piix.c =3D> i440fx.c} | 424 +------------------------------ > hw/timer/i8254_common.c | 40 --- > include/hw/acpi/piix4.h | 6 - > include/hw/i386/pc.h | 37 --- > include/hw/irq.h | 5 - > include/hw/isa/isa.h | 2 + > include/hw/pci-host/i440fx.h | 36 +++ > include/hw/southbridge/piix.h | 74 ++++++ > stubs/pci-host-piix.c | 3 +- > 26 files changed, 699 insertions(+), 683 deletions(-) > create mode 100644 hw/isa/piix3.c > rename hw/pci-host/{piix.c =3D> i440fx.c} (58%) > delete mode 100644 include/hw/acpi/piix4.h > create mode 100644 include/hw/pci-host/i440fx.h > create mode 100644 include/hw/southbridge/piix.h > > -- > 2.21.0 > > > --000000000000becf960595df8c56 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Saturday, October 26, 2019, Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> wrote:
Changes since v2 [0]:
- Use a #define
- Reword one description
- Added review tags (thanks all for reviewing!)

Changes since v1 [1]:
- Removed patch reintroducing DO_UPCAST() use (thuth)
- Took various patches out to reduce series (thuth)
- Added review tags (thanks all for reviewing!)

$ git backport-diff -u pc_split_i440fx_piix-v2
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch=
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respecti= vely

001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from = PC Chipsets'
002/20:[0004] [FC] 'piix4: Add the Reset Control Register'
003/20:[0002] [FC] 'piix4: Add an i8259 Interrupt Controller as specifi= ed in datasheet'
004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"&= #39;
005/20:[----] [--] 'piix4: Rename PIIX4 object to piix4-isa'
006/20:[----] [--] 'piix4: Add an i8257 DMA Controller as specified in = datasheet'
007/20:[----] [-C] 'piix4: Add an i8254 PIT Controller as specified in = datasheet'
008/20:[0004] [FC] 'piix4: Add a MC146818 RTC Controller as specified i= n datasheet'
009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dyn= amically'
010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code= as piix4_create()'
011/20:[----] [-C] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c= '
012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_sta= te_old handlers'
013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
014/20:[0002] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definiti= on'
015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route= Control Registers'
016/20:[----] [-C] 'hw/pci-host/piix: Move i440FX declarations to hw/pc= i-host/i440fx.h'
017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
018/20:[----] [--] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa= /piix3.c'
019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix'= ; as 'i440fx''
020/20:[0004] [FC] 'hw/pci-host/i440fx: Remove the last PIIX3 traces= 9;

Previous cover:

This series is a rework of "piix4: cleanup and improvements" [2]<= br> from Herv=C3=A9, and my "remove i386/pc dependency: PIIX cleanup"= [3].

Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.

This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.

The overall design cleanup is not yet perfect, but enough to post
as a series.

Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.

Based-on: <1572097538-18898-1-git-send-email-pbonzini@redhat.com> to include:
mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of rtc= _init()
https://mid.mail-archive.com/20191018133547.1= 0936-1-philmd@redhat.com

Since Aleksandar offered me to send the pull request [4] I plan to do
it once Paolo's pull [5] is merged.


Philippe,

I a= ttempted the other day the integration of v2 of this series into MIPS pull = request, but couldn't do it - since another series of yours was already= merged, acting on the same code, making rebasing difficult. Now this, v3, = series can't be applied since certain patches in some, on surface, unre= lated series aren't megred, and v3 assumes they are merged.
<= br>
If you send a series, it should preferably be based on the la= test (current) code base, not on some imagined future state.

=
Why did you create this such mess with interdependencies of your= own multiple series, and just right before softfreeze? :( You should have = distributed submitting those series over longer time interval, and absolute= ly avoid, if possible, this hectic around-softfreeze period. You did the op= posite: waited for softfreeze to become close, and sent several interdepend= ant series in matter of days - creating stress without any real technical r= eason.

In case you, for any reason, can't comp= lete this by softfreeze, I advice you not to rush, and postpone the integra= tion to 5.0.

Thanks,
Aleksandar

=C2=A0
Thanks,

Phil.

CI results:
https://travis-ci.org/philmd/qemu/builds/603253987
https://app.shippable.com/github/philmd/qemu/= runs/550/summary/console

[0] https://lists.gnu.org/archive/html/qemu-dev= el/2019-10/msg04662.html
[1] https://lists.gnu.org/archive/html/qemu-dev= el/2019-10/msg03685.html
[2] https://www.mail-archive.com/qemu-devel@nongn= u.org/msg500737.html
[3] https://www.mail-archive.com/qemu-devel@nongn= u.org/msg504081.html
[4] https://lists.gnu.org/archive/html/qemu-dev= el/2019-10/msg04959.html
[5] https://lists.gnu.org/archive/html/qemu-dev= el/2019-10/msg07339.html

Herv=C3=A9 Poussineau (5):
=C2=A0 piix4: Add the Reset Control Register
=C2=A0 piix4: Add an i8259 Interrupt Controller as specified in datasheet =C2=A0 piix4: Rename PIIX4 object to piix4-isa
=C2=A0 piix4: Add an i8257 DMA Controller as specified in datasheet
=C2=A0 piix4: Add an i8254 PIT Controller as specified in datasheet

Philippe Mathieu-Daud=C3=A9 (15):
=C2=A0 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
=C2=A0 Revert "irq: introduce qemu_irq_proxy()"
=C2=A0 piix4: Add a MC146818 RTC Controller as specified in datasheet
=C2=A0 hw/mips/mips_malta: Create IDE hard drive array dynamically
=C2=A0 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create(= )
=C2=A0 hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
=C2=A0 hw/i386: Remove obsolete LoadStateHandler::load_state_old handl= ers
=C2=A0 hw/pci-host/piix: Extract piix3_create()
=C2=A0 hw/pci-host/piix: Move RCR_IOPORT register definition
=C2=A0 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Register= s
=C2=A0 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h =C2=A0 hw/pci-host/piix: Fix code style issues
=C2=A0 hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
=C2=A0 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx&= #39;
=C2=A0 hw/pci-host/i440fx: Remove the last PIIX3 traces

=C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 14 +-
=C2=A0hw/acpi/pcihp.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A02 +-
=C2=A0hw/acpi/piix4.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 42 +--
=C2=A0hw/core/irq.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 |=C2=A0 14 -
=C2=A0hw/i386/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A03 +-
=C2=A0hw/i386/acpi-build.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A05 +-
=C2=A0hw/i386/pc_piix.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 10 +-
=C2=A0hw/i386/xen/xen-hvm.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A05 +-
=C2=A0hw/intc/apic_common.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 49 ----
=C2=A0hw/isa/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0|=C2=A0 =C2=A04 +
=C2=A0hw/isa/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A01 +
=C2=A0hw/isa/piix3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0| 399 +++++++++++++++++++++++++++++
=C2=A0hw/isa/piix4.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0| 151 ++++++++++-
=C2=A0hw/mips/gt64xxx_pci.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A05 +-
=C2=A0hw/mips/mips_malta.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 46 +---
=C2=A0hw/pci-host/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A03 +-
=C2=A0hw/pci-host/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A02 = +-
=C2=A0hw/pci-host/{piix.c =3D> i440fx.c} | 424 +------------------------= ------
=C2=A0hw/timer/i8254_common.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 40 = ---
=C2=A0include/hw/acpi/piix4.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A06 -
=C2=A0include/hw/i386/pc.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 37 ---
=C2=A0include/hw/irq.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0|=C2=A0 =C2=A05 -
=C2=A0include/hw/isa/isa.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A02 +
=C2=A0include/hw/pci-host/i440fx.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 36 +++
=C2=A0include/hw/southbridge/piix.h=C2=A0 =C2=A0 |=C2=A0 74 ++++++
=C2=A0stubs/pci-host-piix.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 =C2=A03 +-
=C2=A026 files changed, 699 insertions(+), 683 deletions(-)
=C2=A0create mode 100644 hw/isa/piix3.c
=C2=A0rename hw/pci-host/{piix.c =3D> i440fx.c} (58%)
=C2=A0delete mode 100644 include/hw/acpi/piix4.h
=C2=A0create mode 100644 include/hw/pci-host/i440fx.h
=C2=A0create mode 100644 include/hw/southbridge/piix.h

--
2.21.0


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