From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 373BAC47404 for ; Wed, 9 Oct 2019 18:08:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE4B721848 for ; Wed, 9 Oct 2019 18:08:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qYwKHRnZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE4B721848 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIGNZ-00031e-GU for qemu-devel@archiver.kernel.org; Wed, 09 Oct 2019 14:08:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55149) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iI8uk-0008TS-U6 for qemu-devel@nongnu.org; Wed, 09 Oct 2019 06:09:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iI8uh-0004nD-M8 for qemu-devel@nongnu.org; Wed, 09 Oct 2019 06:09:50 -0400 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]:39195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iI8uh-0004n3-DI for qemu-devel@nongnu.org; Wed, 09 Oct 2019 06:09:47 -0400 Received: by mail-ot1-x330.google.com with SMTP id s22so1207995otr.6 for ; Wed, 09 Oct 2019 03:09:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=R83R8yhJciWnWovJSyrosPAyeV4SIdlVvQKP3NXnhBI=; b=qYwKHRnZugD6D4qVpdaSuZ3l7T+j5mstb+waqJ1O5LpjTozIq4e9BiktaPb/LIcKOe hUElxEJYaCnLKEvdPuUE04ioUISfE2BRLQjW42QDCpLasm+beoLZmRo5Ub/k1evKtDDD Iy+fA7xfYaA6pjlKCBGhDOv20alG8W/lLKenX3uJOJ9ewKEqbIVzZeuKv0yIEXwHQb/t 8+9Pr4fYsx2vG4A66QP7i+Dt2OOblR4l+rH1h+dZ4WXN1N08jo0Xs/4WOFa3BWoHg0vo EXoS+IL0Wpuu/6kjmEQ1coXM+gtNL2x7yPIfnfQNdya7qsidTrl0wsIt9pdeLg0yy3VS JppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=R83R8yhJciWnWovJSyrosPAyeV4SIdlVvQKP3NXnhBI=; b=bGkiceP6nNWLpdAcCO7x6f3TP/FNa8ISpBs2NrMSQ5QUNTAF1415ghryGSbuFyR//4 4apRdDE67jOlozO8+qYnb/rYSohtAraikdN5PdDpJQ55qUeVgoiIv5g6ouvSTHM0hBwf mvDjbX+GJRcGbyA1cIQCBy7wwTX11x+HOvvQ9qmDtv8lDkvQlwiZsOIpSYYkr8vbpZrh YC0qODRXYybBjIEzqcwlx/GAdgXb9Vsn3JQoZakNjvxvOjVZnirB/SjNTHLsdVmBPNBE njETOSEubWvcE9Wfbh7pIOj35NoH8SWyJzmQqUUCExE0QRJnu/XsPZWPdpNHTsjMj42Y svFA== X-Gm-Message-State: APjAAAXxp1Ik3PzH92QjW8QTEq26RnOX/L6SZkytmZgvy3D1i2NDQ2Hw 5Kvz3FlH3u/xV7rfCvGub+QWjuF7POH75Gz5Qoo= X-Google-Smtp-Source: APXvYqy2Wl4JPaV4XhbThBZlk1McWJofJRLE0+WBWoiZUML5nmwkzv12r574p6wiyzp7bgOPRuvCNhxde3v+i34e85w= X-Received: by 2002:a9d:684c:: with SMTP id c12mr2164303oto.341.1570615786283; Wed, 09 Oct 2019 03:09:46 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:340a:0:0:0:0:0 with HTTP; Wed, 9 Oct 2019 03:09:45 -0700 (PDT) In-Reply-To: References: <87a7ack180.fsf@linaro.org> From: Aleksandar Markovic Date: Wed, 9 Oct 2019 12:09:45 +0200 Message-ID: Subject: Re: [PATCH] target/mips: add gdb xml files To: Mikhail Abakumov Content-Type: multipart/alternative; boundary="000000000000052a690594777ca2" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::330 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "arikalo@wavecomp.com" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Qemu Devel , "amarkovic@wavecomp.com" , "philmd@redhat.com" , "aurelien@aurel32.net" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000052a690594777ca2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wednesday, October 9, 2019, Mikhail Abakumov wrote: > Aleksandar Markovic =D0=BF=D0=B8=D1=81=D0=B0=D0=BB 2019-10-08 16:37: > >> On Monday, October 7, 2019, Alex Benn=C3=A9e >> wrote: >> >> Mikhail Abakumov writes: >>> >>> From: Mikhail Abakumov >>>> >>> >>> Hmm the email got truncated here. >>> >>> >>>> This patch add xml files with gdb registers for mips. >>>> >>>> Signed-off-by: Mikhail Abakumov >>>> --- >>>> configure | 3 ++ >>>> gdb-xml/mips-core.xml | 84 >>>> >>> +++++++++++++++++++++++++++++++++++++++++ >>> >>>> gdb-xml/mips64-core.xml | 84 >>>> +++++++++++++++++++++++++++++++++++++++++ >>>> >>> >>> Otherwise for the configure/xml: >>> >>> Acked-by: Alex Benn=C3=A9e >>> >>> I assume the changes will go in via a MIPS tree. >>> >> >> Yes, this should go via mips tree. Thanks for taking a look. >> >> Mikhail, thanks for this effort. >> >> Is there any way to include MSA registers, possibly in a separate >> file, and in a separate patch? What about a separate file for FPU >> registers? Can you take a look at corresponding solutions for other >> architectures? >> > > Thanks for the feedback. > > Yes, I did it initially. But looking at other architectures, redid it. > Everywhere, one main xml-file is used for registers, described > in the target/gdbstub. And additional ones are appended through > 'gdb_register_coprocessor'. > In the current patch, I made a description of the registers described > only in the target/gdbstub. In the future, I think FPU registers > can be moved to a separate file, but then need to move them from > the mips/gdbstub. Mikhail, Your implementation assumes that 64-bit CPU always has 64-bit FPU, and 32-bit CPU - 32-bit FPU. However, that is not always true. Please see related patch for RISC-V: https://patchew.org/QEMU/20190821162831.27811-1-georg.kotheimer@kernkonzept= .com/ ... and correct your solution in a similar way. Keep also in mind that, in general, gdb xml support should work for all (or at least, almost all) QEMU-supported MIPS CPUs, not just the most common. For example, is your solution correct for R4000 CPU? Is the register layout the same for, for example, "ancient" R4000 and "moderm" I6400? Thanks again! Aleksandar > >> Yours, >> Aleksandar >> >> target/mips/cpu.c | 11 ++++++ >>>> 4 files changed, 182 insertions(+) >>>> create mode 100644 gdb-xml/mips-core.xml >>>> create mode 100644 gdb-xml/mips64-core.xml >>>> >>>> diff --git a/configure b/configure >>>> index 8f8446f52b..5bb2c62194 100755 >>>> --- a/configure >>>> +++ b/configure >>>> @@ -7466,12 +7466,14 @@ case "$target_name" in >>>> mips|mipsel) >>>> mttcg=3D"yes" >>>> TARGET_ARCH=3Dmips >>>> + gdb_xml_files=3D"mips-core.xml" >>>> echo "TARGET_ABI_MIPSO32=3Dy" >> $config_target_mak >>>> ;; >>>> mipsn32|mipsn32el) >>>> mttcg=3D"yes" >>>> TARGET_ARCH=3Dmips64 >>>> TARGET_BASE_ARCH=3Dmips >>>> + gdb_xml_files=3D"mips64-core.xml" >>>> echo "TARGET_ABI_MIPSN32=3Dy" >> $config_target_mak >>>> echo "TARGET_ABI32=3Dy" >> $config_target_mak >>>> ;; >>>> @@ -7479,6 +7481,7 @@ case "$target_name" in >>>> mttcg=3D"yes" >>>> TARGET_ARCH=3Dmips64 >>>> TARGET_BASE_ARCH=3Dmips >>>> + gdb_xml_files=3D"mips64-core.xml" >>>> echo "TARGET_ABI_MIPSN64=3Dy" >> $config_target_mak >>>> ;; >>>> moxie) >>>> diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml >>>> new file mode 100644 >>>> index 0000000000..a46b2993eb >>>> --- /dev/null >>>> +++ b/gdb-xml/mips-core.xml >>>> @@ -0,0 +1,84 @@ >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml >>>> new file mode 100644 >>>> index 0000000000..cc1a15ad56 >>>> --- /dev/null >>>> +++ b/gdb-xml/mips64-core.xml >>>> @@ -0,0 +1,84 @@ >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> + >>>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>>> index bbcf7ca463..014f1db59e 100644 >>>> --- a/target/mips/cpu.c >>>> +++ b/target/mips/cpu.c >>>> @@ -181,6 +181,11 @@ static ObjectClass >>>> >>> *mips_cpu_class_by_name(const >>> >>>> char *cpu_model) >>>> return oc; >>>> } >>>> >>>> +static gchar *mips_gdb_arch_name(CPUState *cs) >>>> +{ >>>> + return g_strdup("mips"); >>>> +} >>>> + >>>> static void mips_cpu_class_init(ObjectClass *c, void *data) >>>> { >>>> MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); >>>> @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass >>>> >>> *c, >>> >>>> void *data) >>>> cc->tlb_fill =3D mips_cpu_tlb_fill; >>>> #endif >>>> >>>> + cc->gdb_arch_name =3D mips_gdb_arch_name; >>>> +#ifdef TARGET_MIPS64 >>>> + cc->gdb_core_xml_file =3D "mips64-core.xml"; >>>> +#else >>>> + cc->gdb_core_xml_file =3D "mips-core.xml"; >>>> +#endif >>>> cc->gdb_num_core_regs =3D 73; >>>> cc->gdb_stop_before_watchpoint =3D true; >>>> } >>>> >>> >>> -- >>> Alex Benn=C3=A9e >>> >> > -- > Mikhail Abakumov > --000000000000052a690594777ca2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Wednesday, October 9, 2019, Mikhail Abakumov <mikhail.abakumov@ispras.ru> wrote:
Aleksandar Markovic =D0=BF=D0=B8=D1=81=D0= =B0=D0=BB 2019-10-08 16:37:
On Monday, October 7, 2019, Alex Benn=C3=A9e <alex.bennee@linaro.org>
wrote:

Mikhail Abakumov <mikhail.abakumov@ispras.ru> writes:

From: Mikhail Abakumov <mikhail.abakumov@ispras>

Hmm the email got truncated here.


This patch add xml files with gdb registers for mips.

Signed-off-by: Mikhail Abakumov <mikhail.abakumov@ispras>
---
configure | 3 ++
gdb-xml/mips-core.xml | 84
+++++++++++++++++++++++++++++++++++++++++
gdb-xml/mips64-core.xml | 84
+++++++++++++++++++++++++++++++++++++++++

Otherwise for the configure/xml:

Acked-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

I assume the changes will go in via a MIPS tree.

Yes, this should go via mips tree. Thanks for taking a look.

Mikhail, thanks for this effort.

Is there any way to include MSA registers, possibly in a separate
file, and in a separate patch? What about a separate file for FPU
registers? Can you take a look at corresponding solutions for other
architectures?

Thanks for the feedback.

Yes, I did it initially. But looking at other architectures, redid it.
Everywhere, one main xml-file is used for registers, described
in the target/gdbstub. And additional ones are appended through
'gdb_register_coprocessor'.
In the current patch, I made a description of the registers described
only in the target/gdbstub. In the future, I think FPU registers
can be moved to a separate file, but then need to move them from
the mips/gdbstub.


Mikhail,

Your implementation assumes that 64-bit CPU always = has 64-bit FPU, and 32-bit CPU - 32-bit FPU. However, that is not always tr= ue.

Please see related patch for RISC-V:


..= . and correct your solution in a similar way.

Keep= also in mind that, in general, gdb xml support should work for all (or at = least, almost all) QEMU-supported MIPS CPUs, not just the most common. For = example, is your solution correct for R4000 CPU? Is the register layout the= same for, for example, "ancient" R4000 and "moderm" I6= 400?

Thanks again!

Aleksa= ndar





Yours,
Aleksandar

target/mips/cpu.c | 11 ++++++
4 files changed, 182 insertions(+)
create mode 100644 gdb-xml/mips-core.xml
create mode 100644 gdb-xml/mips64-core.xml

diff --git a/configure b/configure
index 8f8446f52b..5bb2c62194 100755
--- a/configure
+++ b/configure
@@ -7466,12 +7466,14 @@ case "$target_name" in
mips|mipsel)
mttcg=3D"yes"
TARGET_ARCH=3Dmips
+ gdb_xml_files=3D"mips-core.xml"
echo "TARGET_ABI_MIPSO32=3Dy" >> $config_target_mak
;;
mipsn32|mipsn32el)
mttcg=3D"yes"
TARGET_ARCH=3Dmips64
TARGET_BASE_ARCH=3Dmips
+ gdb_xml_files=3D"mips64-core.xml"
echo "TARGET_ABI_MIPSN32=3Dy" >> $config_target_mak
echo "TARGET_ABI32=3Dy" >> $config_target_mak
;;
@@ -7479,6 +7481,7 @@ case "$target_name" in
mttcg=3D"yes"
TARGET_ARCH=3Dmips64
TARGET_BASE_ARCH=3Dmips
+ gdb_xml_files=3D"mips64-core.xml"
echo "TARGET_ABI_MIPSN64=3Dy" >> $config_target_mak
;;
moxie)
diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml
new file mode 100644
index 0000000000..a46b2993eb
--- /dev/null
+++ b/gdb-xml/mips-core.xml
@@ -0,0 +1,84 @@
+<?xml version=3D"1.0"?>
+<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without
modification,
+ are permitted in any medium without royalty provided the
copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name=3D"org.gnu.gdb.mips">
+ <reg name=3D"zero" bitsize=3D"32"/>
+ <reg name=3D"at" bitsize=3D"32"/>
+ <reg name=3D"v0" bitsize=3D"32"/>
+ <reg name=3D"v1" bitsize=3D"32"/>
+ <reg name=3D"a0" bitsize=3D"32"/>
+ <reg name=3D"a1" bitsize=3D"32"/>
+ <reg name=3D"a2" bitsize=3D"32"/>
+ <reg name=3D"a3" bitsize=3D"32"/>
+ <reg name=3D"t0" bitsize=3D"32"/>
+ <reg name=3D"t1" bitsize=3D"32"/>
+ <reg name=3D"t2" bitsize=3D"32"/>
+ <reg name=3D"t3" bitsize=3D"32"/>
+ <reg name=3D"t4" bitsize=3D"32"/>
+ <reg name=3D"t5" bitsize=3D"32"/>
+ <reg name=3D"t6" bitsize=3D"32"/>
+ <reg name=3D"t7" bitsize=3D"32"/>
+ <reg name=3D"s0" bitsize=3D"32"/>
+ <reg name=3D"s1" bitsize=3D"32"/>
+ <reg name=3D"s2" bitsize=3D"32"/>
+ <reg name=3D"s3" bitsize=3D"32"/>
+ <reg name=3D"s4" bitsize=3D"32"/>
+ <reg name=3D"s5" bitsize=3D"32"/>
+ <reg name=3D"s6" bitsize=3D"32"/>
+ <reg name=3D"s7" bitsize=3D"32"/>
+ <reg name=3D"t8" bitsize=3D"32"/>
+ <reg name=3D"t9" bitsize=3D"32"/>
+ <reg name=3D"k0" bitsize=3D"32"/>
+ <reg name=3D"k1" bitsize=3D"32"/>
+ <reg name=3D"gp" bitsize=3D"32"/>
+ <reg name=3D"sp" bitsize=3D"32"/>
+ <reg name=3D"s8" bitsize=3D"32"/>
+ <reg name=3D"ra" bitsize=3D"32"/>
+ <reg name=3D"sr" bitsize=3D"32"/>
+ <reg name=3D"lo" bitsize=3D"32"/>
+ <reg name=3D"hi" bitsize=3D"32"/>
+ <reg name=3D"bad" bitsize=3D"32"/>
+ <reg name=3D"cause" bitsize=3D"32"/>
+ <reg name=3D"pc" bitsize=3D"32"/>
+
+ <reg name=3D"f0" bitsize=3D"32" regnum=3D"38&= quot;/>
+ <reg name=3D"f1" bitsize=3D"32"/>
+ <reg name=3D"f2" bitsize=3D"32"/>
+ <reg name=3D"f3" bitsize=3D"32"/>
+ <reg name=3D"f4" bitsize=3D"32"/>
+ <reg name=3D"f5" bitsize=3D"32"/>
+ <reg name=3D"f6" bitsize=3D"32"/>
+ <reg name=3D"f7" bitsize=3D"32"/>
+ <reg name=3D"f8" bitsize=3D"32"/>
+ <reg name=3D"f9" bitsize=3D"32"/>
+ <reg name=3D"f10" bitsize=3D"32"/>
+ <reg name=3D"f11" bitsize=3D"32"/>
+ <reg name=3D"f12" bitsize=3D"32"/>
+ <reg name=3D"f13" bitsize=3D"32"/>
+ <reg name=3D"f14" bitsize=3D"32"/>
+ <reg name=3D"f15" bitsize=3D"32"/>
+ <reg name=3D"f16" bitsize=3D"32"/>
+ <reg name=3D"f17" bitsize=3D"32"/>
+ <reg name=3D"f18" bitsize=3D"32"/>
+ <reg name=3D"f19" bitsize=3D"32"/>
+ <reg name=3D"f20" bitsize=3D"32"/>
+ <reg name=3D"f21" bitsize=3D"32"/>
+ <reg name=3D"f22" bitsize=3D"32"/>
+ <reg name=3D"f23" bitsize=3D"32"/>
+ <reg name=3D"f24" bitsize=3D"32"/>
+ <reg name=3D"f25" bitsize=3D"32"/>
+ <reg name=3D"f26" bitsize=3D"32"/>
+ <reg name=3D"f27" bitsize=3D"32"/>
+ <reg name=3D"f28" bitsize=3D"32"/>
+ <reg name=3D"f29" bitsize=3D"32"/>
+ <reg name=3D"f30" bitsize=3D"32"/>
+ <reg name=3D"f31" bitsize=3D"32"/>
+ <reg name=3D"fsr" bitsize=3D"32" group=3D"flo= at"/>
+ <reg name=3D"fir" bitsize=3D"32" group=3D"flo= at"/>
+ <reg name=3D"fp" bitsize=3D"32" group=3D"floa= t"/>
+</feature>
diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml
new file mode 100644
index 0000000000..cc1a15ad56
--- /dev/null
+++ b/gdb-xml/mips64-core.xml
@@ -0,0 +1,84 @@
+<?xml version=3D"1.0"?>
+<!-- Copyright (C) 2010-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without
modification,
+ are permitted in any medium without royalty provided the
copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name=3D"org.gnu.gdb.mips64">
+ <reg name=3D"zero" bitsize=3D"64"/>
+ <reg name=3D"at" bitsize=3D"64"/>
+ <reg name=3D"v0" bitsize=3D"64"/>
+ <reg name=3D"v1" bitsize=3D"64"/>
+ <reg name=3D"a0" bitsize=3D"64"/>
+ <reg name=3D"a1" bitsize=3D"64"/>
+ <reg name=3D"a2" bitsize=3D"64"/>
+ <reg name=3D"a3" bitsize=3D"64"/>
+ <reg name=3D"t0" bitsize=3D"64"/>
+ <reg name=3D"t1" bitsize=3D"64"/>
+ <reg name=3D"t2" bitsize=3D"64"/>
+ <reg name=3D"t3" bitsize=3D"64"/>
+ <reg name=3D"t4" bitsize=3D"64"/>
+ <reg name=3D"t5" bitsize=3D"64"/>
+ <reg name=3D"t6" bitsize=3D"64"/>
+ <reg name=3D"t7" bitsize=3D"64"/>
+ <reg name=3D"s0" bitsize=3D"64"/>
+ <reg name=3D"s1" bitsize=3D"64"/>
+ <reg name=3D"s2" bitsize=3D"64"/>
+ <reg name=3D"s3" bitsize=3D"64"/>
+ <reg name=3D"s4" bitsize=3D"64"/>
+ <reg name=3D"s5" bitsize=3D"64"/>
+ <reg name=3D"s6" bitsize=3D"64"/>
+ <reg name=3D"s7" bitsize=3D"64"/>
+ <reg name=3D"t8" bitsize=3D"64"/>
+ <reg name=3D"t9" bitsize=3D"64"/>
+ <reg name=3D"k0" bitsize=3D"64"/>
+ <reg name=3D"k1" bitsize=3D"64"/>
+ <reg name=3D"gp" bitsize=3D"64"/>
+ <reg name=3D"sp" bitsize=3D"64"/>
+ <reg name=3D"s8" bitsize=3D"64"/>
+ <reg name=3D"ra" bitsize=3D"64"/>
+ <reg name=3D"sr" bitsize=3D"64"/>
+ <reg name=3D"lo" bitsize=3D"64"/>
+ <reg name=3D"hi" bitsize=3D"64"/>
+ <reg name=3D"bad" bitsize=3D"64"/>
+ <reg name=3D"cause" bitsize=3D"64"/>
+ <reg name=3D"pc" bitsize=3D"64"/>
+
+ <reg name=3D"f0" bitsize=3D"64" regnum=3D"38&= quot;/>
+ <reg name=3D"f1" bitsize=3D"64"/>
+ <reg name=3D"f2" bitsize=3D"64"/>
+ <reg name=3D"f3" bitsize=3D"64"/>
+ <reg name=3D"f4" bitsize=3D"64"/>
+ <reg name=3D"f5" bitsize=3D"64"/>
+ <reg name=3D"f6" bitsize=3D"64"/>
+ <reg name=3D"f7" bitsize=3D"64"/>
+ <reg name=3D"f8" bitsize=3D"64"/>
+ <reg name=3D"f9" bitsize=3D"64"/>
+ <reg name=3D"f10" bitsize=3D"64"/>
+ <reg name=3D"f11" bitsize=3D"64"/>
+ <reg name=3D"f12" bitsize=3D"64"/>
+ <reg name=3D"f13" bitsize=3D"64"/>
+ <reg name=3D"f14" bitsize=3D"64"/>
+ <reg name=3D"f15" bitsize=3D"64"/>
+ <reg name=3D"f16" bitsize=3D"64"/>
+ <reg name=3D"f17" bitsize=3D"64"/>
+ <reg name=3D"f18" bitsize=3D"64"/>
+ <reg name=3D"f19" bitsize=3D"64"/>
+ <reg name=3D"f20" bitsize=3D"64"/>
+ <reg name=3D"f21" bitsize=3D"64"/>
+ <reg name=3D"f22" bitsize=3D"64"/>
+ <reg name=3D"f23" bitsize=3D"64"/>
+ <reg name=3D"f24" bitsize=3D"64"/>
+ <reg name=3D"f25" bitsize=3D"64"/>
+ <reg name=3D"f26" bitsize=3D"64"/>
+ <reg name=3D"f27" bitsize=3D"64"/>
+ <reg name=3D"f28" bitsize=3D"64"/>
+ <reg name=3D"f29" bitsize=3D"64"/>
+ <reg name=3D"f30" bitsize=3D"64"/>
+ <reg name=3D"f31" bitsize=3D"64"/>
+ <reg name=3D"fsr" bitsize=3D"64" group=3D"flo= at"/>
+ <reg name=3D"fir" bitsize=3D"64" group=3D"flo= at"/>
+ <reg name=3D"fp" bitsize=3D"64" group=3D"floa= t"/>
+</feature>
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bbcf7ca463..014f1db59e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -181,6 +181,11 @@ static ObjectClass
*mips_cpu_class_by_name(const
char *cpu_model)
return oc;
}

+static gchar *mips_gdb_arch_name(CPUState *cs)
+{
+ return g_strdup("mips");
+}
+
static void mips_cpu_class_init(ObjectClass *c, void *data)
{
MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c);
@@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass
*c,
void *data)
cc->tlb_fill =3D mips_cpu_tlb_fill;
#endif

+ cc->gdb_arch_name =3D mips_gdb_arch_name;
+#ifdef TARGET_MIPS64
+ cc->gdb_core_xml_file =3D "mips64-core.xml";
+#else
+ cc->gdb_core_xml_file =3D "mips-core.xml";
+#endif
cc->gdb_num_core_regs =3D 73;
cc->gdb_stop_before_watchpoint =3D true;
}

--
Alex Benn=C3=A9e

--
Mikhail Abakumov
--000000000000052a690594777ca2--