From: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Aleksandar Rikalo" <arikalo@wavecomp.com>,
qemu-devel@nongnu.org, "Hervé Poussineau" <hpoussin@reactos.org>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH 02/10] hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues
Date: Tue, 25 Jun 2019 02:21:58 +0200 [thread overview]
Message-ID: <CAL1e-=juYo93V2LkhPiE6-Ud0sHEx9u-EBMPbQkk4g-wSZeq+Q@mail.gmail.com> (raw)
In-Reply-To: <20190624222844.26584-3-f4bug@amsat.org>
On Jun 25, 2019 12:30 AM, "Philippe Mathieu-Daudé" <f4bug@amsat.org> wrote:
>
> Since we'll move this code around, fix its style first:
>
> ERROR: code indent should never use tabs
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> hw/mips/gt64xxx_pci.c | 312 +++++++++++++++++++++---------------------
> 1 file changed, 156 insertions(+), 156 deletions(-)
>
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index c0924646b5..bbd719f091 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -38,192 +38,192 @@
> #define DPRINTF(fmt, ...)
> #endif
>
> -#define GT_REGS (0x1000 >> 2)
> +#define GT_REGS (0x1000 >> 2)
>
> /* CPU Configuration */
> -#define GT_CPU (0x000 >> 2)
> -#define GT_MULTI (0x120 >> 2)
> +#define GT_CPU (0x000 >> 2)
> +#define GT_MULTI (0x120 >> 2)
>
> /* CPU Address Decode */
> -#define GT_SCS10LD (0x008 >> 2)
> -#define GT_SCS10HD (0x010 >> 2)
> -#define GT_SCS32LD (0x018 >> 2)
> -#define GT_SCS32HD (0x020 >> 2)
> -#define GT_CS20LD (0x028 >> 2)
> -#define GT_CS20HD (0x030 >> 2)
> -#define GT_CS3BOOTLD (0x038 >> 2)
> -#define GT_CS3BOOTHD (0x040 >> 2)
> -#define GT_PCI0IOLD (0x048 >> 2)
> -#define GT_PCI0IOHD (0x050 >> 2)
> -#define GT_PCI0M0LD (0x058 >> 2)
> -#define GT_PCI0M0HD (0x060 >> 2)
> -#define GT_PCI0M1LD (0x080 >> 2)
> -#define GT_PCI0M1HD (0x088 >> 2)
> -#define GT_PCI1IOLD (0x090 >> 2)
> -#define GT_PCI1IOHD (0x098 >> 2)
> -#define GT_PCI1M0LD (0x0a0 >> 2)
> -#define GT_PCI1M0HD (0x0a8 >> 2)
> -#define GT_PCI1M1LD (0x0b0 >> 2)
> -#define GT_PCI1M1HD (0x0b8 >> 2)
> -#define GT_ISD (0x068 >> 2)
> -
> -#define GT_SCS10AR (0x0d0 >> 2)
> -#define GT_SCS32AR (0x0d8 >> 2)
> -#define GT_CS20R (0x0e0 >> 2)
> -#define GT_CS3BOOTR (0x0e8 >> 2)
> -
> -#define GT_PCI0IOREMAP (0x0f0 >> 2)
> -#define GT_PCI0M0REMAP (0x0f8 >> 2)
> -#define GT_PCI0M1REMAP (0x100 >> 2)
> -#define GT_PCI1IOREMAP (0x108 >> 2)
> -#define GT_PCI1M0REMAP (0x110 >> 2)
> -#define GT_PCI1M1REMAP (0x118 >> 2)
> +#define GT_SCS10LD (0x008 >> 2)
> +#define GT_SCS10HD (0x010 >> 2)
> +#define GT_SCS32LD (0x018 >> 2)
> +#define GT_SCS32HD (0x020 >> 2)
> +#define GT_CS20LD (0x028 >> 2)
> +#define GT_CS20HD (0x030 >> 2)
> +#define GT_CS3BOOTLD (0x038 >> 2)
> +#define GT_CS3BOOTHD (0x040 >> 2)
> +#define GT_PCI0IOLD (0x048 >> 2)
> +#define GT_PCI0IOHD (0x050 >> 2)
> +#define GT_PCI0M0LD (0x058 >> 2)
> +#define GT_PCI0M0HD (0x060 >> 2)
> +#define GT_PCI0M1LD (0x080 >> 2)
> +#define GT_PCI0M1HD (0x088 >> 2)
> +#define GT_PCI1IOLD (0x090 >> 2)
> +#define GT_PCI1IOHD (0x098 >> 2)
> +#define GT_PCI1M0LD (0x0a0 >> 2)
> +#define GT_PCI1M0HD (0x0a8 >> 2)
> +#define GT_PCI1M1LD (0x0b0 >> 2)
> +#define GT_PCI1M1HD (0x0b8 >> 2)
> +#define GT_ISD (0x068 >> 2)
> +
> +#define GT_SCS10AR (0x0d0 >> 2)
> +#define GT_SCS32AR (0x0d8 >> 2)
> +#define GT_CS20R (0x0e0 >> 2)
> +#define GT_CS3BOOTR (0x0e8 >> 2)
> +
> +#define GT_PCI0IOREMAP (0x0f0 >> 2)
> +#define GT_PCI0M0REMAP (0x0f8 >> 2)
> +#define GT_PCI0M1REMAP (0x100 >> 2)
> +#define GT_PCI1IOREMAP (0x108 >> 2)
> +#define GT_PCI1M0REMAP (0x110 >> 2)
> +#define GT_PCI1M1REMAP (0x118 >> 2)
>
> /* CPU Error Report */
> -#define GT_CPUERR_ADDRLO (0x070 >> 2)
> -#define GT_CPUERR_ADDRHI (0x078 >> 2)
> -#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A
only */
> -#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A
only */
> -#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A
only */
> +#define GT_CPUERR_ADDRLO (0x070 >> 2)
> +#define GT_CPUERR_ADDRHI (0x078 >> 2)
> +#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
> +#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
> +#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
>
> /* CPU Sync Barrier */
> -#define GT_PCI0SYNC (0x0c0 >> 2)
> -#define GT_PCI1SYNC (0x0c8 >> 2)
> +#define GT_PCI0SYNC (0x0c0 >> 2)
> +#define GT_PCI1SYNC (0x0c8 >> 2)
>
> /* SDRAM and Device Address Decode */
> -#define GT_SCS0LD (0x400 >> 2)
> -#define GT_SCS0HD (0x404 >> 2)
> -#define GT_SCS1LD (0x408 >> 2)
> -#define GT_SCS1HD (0x40c >> 2)
> -#define GT_SCS2LD (0x410 >> 2)
> -#define GT_SCS2HD (0x414 >> 2)
> -#define GT_SCS3LD (0x418 >> 2)
> -#define GT_SCS3HD (0x41c >> 2)
> -#define GT_CS0LD (0x420 >> 2)
> -#define GT_CS0HD (0x424 >> 2)
> -#define GT_CS1LD (0x428 >> 2)
> -#define GT_CS1HD (0x42c >> 2)
> -#define GT_CS2LD (0x430 >> 2)
> -#define GT_CS2HD (0x434 >> 2)
> -#define GT_CS3LD (0x438 >> 2)
> -#define GT_CS3HD (0x43c >> 2)
> -#define GT_BOOTLD (0x440 >> 2)
> -#define GT_BOOTHD (0x444 >> 2)
> -#define GT_ADERR (0x470 >> 2)
> +#define GT_SCS0LD (0x400 >> 2)
> +#define GT_SCS0HD (0x404 >> 2)
> +#define GT_SCS1LD (0x408 >> 2)
> +#define GT_SCS1HD (0x40c >> 2)
> +#define GT_SCS2LD (0x410 >> 2)
> +#define GT_SCS2HD (0x414 >> 2)
> +#define GT_SCS3LD (0x418 >> 2)
> +#define GT_SCS3HD (0x41c >> 2)
> +#define GT_CS0LD (0x420 >> 2)
> +#define GT_CS0HD (0x424 >> 2)
> +#define GT_CS1LD (0x428 >> 2)
> +#define GT_CS1HD (0x42c >> 2)
> +#define GT_CS2LD (0x430 >> 2)
> +#define GT_CS2HD (0x434 >> 2)
> +#define GT_CS3LD (0x438 >> 2)
> +#define GT_CS3HD (0x43c >> 2)
> +#define GT_BOOTLD (0x440 >> 2)
> +#define GT_BOOTHD (0x444 >> 2)
> +#define GT_ADERR (0x470 >> 2)
>
> /* SDRAM Configuration */
> -#define GT_SDRAM_CFG (0x448 >> 2)
> -#define GT_SDRAM_OPMODE (0x474 >> 2)
> -#define GT_SDRAM_BM (0x478 >> 2)
> -#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
> +#define GT_SDRAM_CFG (0x448 >> 2)
> +#define GT_SDRAM_OPMODE (0x474 >> 2)
> +#define GT_SDRAM_BM (0x478 >> 2)
> +#define GT_SDRAM_ADDRDECODE (0x47c >> 2)
>
> /* SDRAM Parameters */
> -#define GT_SDRAM_B0 (0x44c >> 2)
> -#define GT_SDRAM_B1 (0x450 >> 2)
> -#define GT_SDRAM_B2 (0x454 >> 2)
> -#define GT_SDRAM_B3 (0x458 >> 2)
> +#define GT_SDRAM_B0 (0x44c >> 2)
> +#define GT_SDRAM_B1 (0x450 >> 2)
> +#define GT_SDRAM_B2 (0x454 >> 2)
> +#define GT_SDRAM_B3 (0x458 >> 2)
>
> /* Device Parameters */
> -#define GT_DEV_B0 (0x45c >> 2)
> -#define GT_DEV_B1 (0x460 >> 2)
> -#define GT_DEV_B2 (0x464 >> 2)
> -#define GT_DEV_B3 (0x468 >> 2)
> -#define GT_DEV_BOOT (0x46c >> 2)
> +#define GT_DEV_B0 (0x45c >> 2)
> +#define GT_DEV_B1 (0x460 >> 2)
> +#define GT_DEV_B2 (0x464 >> 2)
> +#define GT_DEV_B3 (0x468 >> 2)
> +#define GT_DEV_BOOT (0x46c >> 2)
>
> /* ECC */
> -#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A
only */
> -#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A
only */
> -#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A
only */
> -#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A
only */
> -#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A
only */
> +#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
> +#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
> +#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
> +#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
> +#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
>
> /* DMA Record */
> -#define GT_DMA0_CNT (0x800 >> 2)
> -#define GT_DMA1_CNT (0x804 >> 2)
> -#define GT_DMA2_CNT (0x808 >> 2)
> -#define GT_DMA3_CNT (0x80c >> 2)
> -#define GT_DMA0_SA (0x810 >> 2)
> -#define GT_DMA1_SA (0x814 >> 2)
> -#define GT_DMA2_SA (0x818 >> 2)
> -#define GT_DMA3_SA (0x81c >> 2)
> -#define GT_DMA0_DA (0x820 >> 2)
> -#define GT_DMA1_DA (0x824 >> 2)
> -#define GT_DMA2_DA (0x828 >> 2)
> -#define GT_DMA3_DA (0x82c >> 2)
> -#define GT_DMA0_NEXT (0x830 >> 2)
> -#define GT_DMA1_NEXT (0x834 >> 2)
> -#define GT_DMA2_NEXT (0x838 >> 2)
> -#define GT_DMA3_NEXT (0x83c >> 2)
> -#define GT_DMA0_CUR (0x870 >> 2)
> -#define GT_DMA1_CUR (0x874 >> 2)
> -#define GT_DMA2_CUR (0x878 >> 2)
> -#define GT_DMA3_CUR (0x87c >> 2)
> +#define GT_DMA0_CNT (0x800 >> 2)
> +#define GT_DMA1_CNT (0x804 >> 2)
> +#define GT_DMA2_CNT (0x808 >> 2)
> +#define GT_DMA3_CNT (0x80c >> 2)
> +#define GT_DMA0_SA (0x810 >> 2)
> +#define GT_DMA1_SA (0x814 >> 2)
> +#define GT_DMA2_SA (0x818 >> 2)
> +#define GT_DMA3_SA (0x81c >> 2)
> +#define GT_DMA0_DA (0x820 >> 2)
> +#define GT_DMA1_DA (0x824 >> 2)
> +#define GT_DMA2_DA (0x828 >> 2)
> +#define GT_DMA3_DA (0x82c >> 2)
> +#define GT_DMA0_NEXT (0x830 >> 2)
> +#define GT_DMA1_NEXT (0x834 >> 2)
> +#define GT_DMA2_NEXT (0x838 >> 2)
> +#define GT_DMA3_NEXT (0x83c >> 2)
> +#define GT_DMA0_CUR (0x870 >> 2)
> +#define GT_DMA1_CUR (0x874 >> 2)
> +#define GT_DMA2_CUR (0x878 >> 2)
> +#define GT_DMA3_CUR (0x87c >> 2)
>
> /* DMA Channel Control */
> -#define GT_DMA0_CTRL (0x840 >> 2)
> -#define GT_DMA1_CTRL (0x844 >> 2)
> -#define GT_DMA2_CTRL (0x848 >> 2)
> -#define GT_DMA3_CTRL (0x84c >> 2)
> +#define GT_DMA0_CTRL (0x840 >> 2)
> +#define GT_DMA1_CTRL (0x844 >> 2)
> +#define GT_DMA2_CTRL (0x848 >> 2)
> +#define GT_DMA3_CTRL (0x84c >> 2)
>
> /* DMA Arbiter */
> -#define GT_DMA_ARB (0x860 >> 2)
> +#define GT_DMA_ARB (0x860 >> 2)
>
> /* Timer/Counter */
> -#define GT_TC0 (0x850 >> 2)
> -#define GT_TC1 (0x854 >> 2)
> -#define GT_TC2 (0x858 >> 2)
> -#define GT_TC3 (0x85c >> 2)
> -#define GT_TC_CONTROL (0x864 >> 2)
> +#define GT_TC0 (0x850 >> 2)
> +#define GT_TC1 (0x854 >> 2)
> +#define GT_TC2 (0x858 >> 2)
> +#define GT_TC3 (0x85c >> 2)
> +#define GT_TC_CONTROL (0x864 >> 2)
>
> /* PCI Internal */
> -#define GT_PCI0_CMD (0xc00 >> 2)
> -#define GT_PCI0_TOR (0xc04 >> 2)
> -#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
> -#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
> -#define GT_PCI0_BS_CS20 (0xc10 >> 2)
> -#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
> -#define GT_PCI1_IACK (0xc30 >> 2)
> -#define GT_PCI0_IACK (0xc34 >> 2)
> -#define GT_PCI0_BARE (0xc3c >> 2)
> -#define GT_PCI0_PREFMBR (0xc40 >> 2)
> -#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
> -#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
> -#define GT_PCI0_CS20_BAR (0xc50 >> 2)
> -#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
> -#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
> -#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
> -#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
> -#define GT_PCI1_CMD (0xc80 >> 2)
> -#define GT_PCI1_TOR (0xc84 >> 2)
> -#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
> -#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
> -#define GT_PCI1_BS_CS20 (0xc90 >> 2)
> -#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
> -#define GT_PCI1_BARE (0xcbc >> 2)
> -#define GT_PCI1_PREFMBR (0xcc0 >> 2)
> -#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
> -#define GT_PCI1_SCS32_BAR (0xccc >> 2)
> -#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
> -#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
> -#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
> -#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
> -#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
> -#define GT_PCI1_CFGADDR (0xcf0 >> 2)
> -#define GT_PCI1_CFGDATA (0xcf4 >> 2)
> -#define GT_PCI0_CFGADDR (0xcf8 >> 2)
> -#define GT_PCI0_CFGDATA (0xcfc >> 2)
> +#define GT_PCI0_CMD (0xc00 >> 2)
> +#define GT_PCI0_TOR (0xc04 >> 2)
> +#define GT_PCI0_BS_SCS10 (0xc08 >> 2)
> +#define GT_PCI0_BS_SCS32 (0xc0c >> 2)
> +#define GT_PCI0_BS_CS20 (0xc10 >> 2)
> +#define GT_PCI0_BS_CS3BT (0xc14 >> 2)
> +#define GT_PCI1_IACK (0xc30 >> 2)
> +#define GT_PCI0_IACK (0xc34 >> 2)
> +#define GT_PCI0_BARE (0xc3c >> 2)
> +#define GT_PCI0_PREFMBR (0xc40 >> 2)
> +#define GT_PCI0_SCS10_BAR (0xc48 >> 2)
> +#define GT_PCI0_SCS32_BAR (0xc4c >> 2)
> +#define GT_PCI0_CS20_BAR (0xc50 >> 2)
> +#define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
> +#define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
> +#define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
> +#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
> +#define GT_PCI1_CMD (0xc80 >> 2)
> +#define GT_PCI1_TOR (0xc84 >> 2)
> +#define GT_PCI1_BS_SCS10 (0xc88 >> 2)
> +#define GT_PCI1_BS_SCS32 (0xc8c >> 2)
> +#define GT_PCI1_BS_CS20 (0xc90 >> 2)
> +#define GT_PCI1_BS_CS3BT (0xc94 >> 2)
> +#define GT_PCI1_BARE (0xcbc >> 2)
> +#define GT_PCI1_PREFMBR (0xcc0 >> 2)
> +#define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
> +#define GT_PCI1_SCS32_BAR (0xccc >> 2)
> +#define GT_PCI1_CS20_BAR (0xcd0 >> 2)
> +#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
> +#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
> +#define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
> +#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
> +#define GT_PCI1_CFGADDR (0xcf0 >> 2)
> +#define GT_PCI1_CFGDATA (0xcf4 >> 2)
> +#define GT_PCI0_CFGADDR (0xcf8 >> 2)
> +#define GT_PCI0_CFGDATA (0xcfc >> 2)
>
> /* Interrupts */
> -#define GT_INTRCAUSE (0xc18 >> 2)
> -#define GT_INTRMASK (0xc1c >> 2)
> -#define GT_PCI0_ICMASK (0xc24 >> 2)
> -#define GT_PCI0_SERR0MASK (0xc28 >> 2)
> -#define GT_CPU_INTSEL (0xc70 >> 2)
> -#define GT_PCI0_INTSEL (0xc74 >> 2)
> -#define GT_HINTRCAUSE (0xc98 >> 2)
> -#define GT_HINTRMASK (0xc9c >> 2)
> -#define GT_PCI0_HICMASK (0xca4 >> 2)
> -#define GT_PCI1_SERR1MASK (0xca8 >> 2)
> +#define GT_INTRCAUSE (0xc18 >> 2)
> +#define GT_INTRMASK (0xc1c >> 2)
> +#define GT_PCI0_ICMASK (0xc24 >> 2)
> +#define GT_PCI0_SERR0MASK (0xc28 >> 2)
> +#define GT_CPU_INTSEL (0xc70 >> 2)
> +#define GT_PCI0_INTSEL (0xc74 >> 2)
> +#define GT_HINTRCAUSE (0xc98 >> 2)
> +#define GT_HINTRMASK (0xc9c >> 2)
> +#define GT_PCI0_HICMASK (0xca4 >> 2)
> +#define GT_PCI1_SERR1MASK (0xca8 >> 2)
>
> #define PCI_MAPPING_ENTRY(regname) \
> hwaddr regname ##_start; \
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2019-06-25 0:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 22:28 [Qemu-devel] [PATCH 00/10] hw/pci-host: Clean the GT64120 north bridge Philippe Mathieu-Daudé
2019-06-24 22:28 ` [Qemu-devel] [PATCH 01/10] hw/mips/gt64xxx_pci: Fix multiline comment syntax Philippe Mathieu-Daudé
2019-06-25 0:20 ` Aleksandar Markovic
2019-06-24 22:28 ` [Qemu-devel] [PATCH 02/10] hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues Philippe Mathieu-Daudé
2019-06-25 0:21 ` Aleksandar Markovic [this message]
2019-06-24 22:28 ` [Qemu-devel] [PATCH 03/10] hw/mips/gt64xxx_pci: Fix 'braces' " Philippe Mathieu-Daudé
2019-06-25 0:22 ` Aleksandar Markovic
2019-06-24 22:28 ` [Qemu-devel] [PATCH 04/10] hw/mips/gt64xxx_pci: Fix 'spaces' " Philippe Mathieu-Daudé
2019-06-25 0:23 ` Aleksandar Markovic
2019-06-24 22:28 ` [Qemu-devel] [PATCH 05/10] hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf() Philippe Mathieu-Daudé
2019-06-25 0:37 ` Aleksandar Markovic
2019-06-25 7:14 ` Philippe Mathieu-Daudé
2019-06-25 18:16 ` Aleksandar Markovic
2019-06-24 22:28 ` [Qemu-devel] [PATCH 06/10] hw/mips/gt64xxx_pci: Convert debug printf()s to trace events Philippe Mathieu-Daudé
2019-06-25 0:40 ` Aleksandar Markovic
2019-06-25 10:00 ` Philippe Mathieu-Daudé
2019-06-25 18:17 ` Aleksandar Markovic
2019-06-24 22:28 ` [Qemu-devel] [PATCH 07/10] hw/mips/gt64xxx_pci: Align the pci0-mem size Philippe Mathieu-Daudé
2019-06-25 0:43 ` Aleksandar Markovic
2019-06-25 7:41 ` Philippe Mathieu-Daudé
2019-06-24 22:28 ` [Qemu-devel] [PATCH 08/10] hw/mips/gt64xxx_pci: Add a 'cpu_big_endian' qdev property Philippe Mathieu-Daudé
2019-06-24 22:28 ` [Qemu-devel] [PATCH 09/10] hw/mips/gt64xxx_pci: Move it to hw/pci-host/ Philippe Mathieu-Daudé
2019-06-24 22:28 ` [Qemu-devel] [RFC PATCH 10/10] hw/pci-host/gt64120: Clean the decoded address space Philippe Mathieu-Daudé
2019-07-01 18:06 ` Philippe Mathieu-Daudé
2019-07-17 20:58 ` Paul Burton
2019-07-01 17:16 ` [Qemu-devel] [PATCH 00/10] hw/pci-host: Clean the GT64120 north bridge Aleksandar Markovic
2019-07-01 17:45 ` Philippe Mathieu-Daudé
2019-07-01 18:39 ` Aleksandar Markovic
2019-07-02 8:50 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAL1e-=juYo93V2LkhPiE6-Ud0sHEx9u-EBMPbQkk4g-wSZeq+Q@mail.gmail.com' \
--to=aleksandar.m.mail@gmail.com \
--cc=amarkovic@wavecomp.com \
--cc=arikalo@wavecomp.com \
--cc=atar4qemu@gmail.com \
--cc=aurelien@aurel32.net \
--cc=f4bug@amsat.org \
--cc=hpoussin@reactos.org \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).