Re: [Qemu-devel] MMU Modes

[Xin Tong <xerox.time.tech@gmail.com>]

I am investigating how LW is emulated from target-mips on x86 host.
However, i can not find where the OFFSET is passed in.

    case OPC_LW:
        save_cpu_state(ctx, 0);
        op_ld_lw(t0, t0, ctx);
        gen_store_gpr(t0, rt);
        opn = "lw";
        break;

       ||
       ||
      \||/

 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx)   \
 {                                                                         \
     tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                        \
 }

I think ctx->mem_idx here contains the MMU modes.

       ||
       ||
      \||/

 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
 {
  #if TARGET_LONG_BITS == 32
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
  #else
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
                    TCGV_HIGH(addr), mem_index);
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
  #endif
  }


       ||
       ||
      \||/


 case INDEX_op_qemu_ld32:
       tcg_out_qemu_ld(s, args, 2);
       break;


Thanks


Xin



On Fri, Jan 6, 2012 at 7:55 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 6 January 2012 12:45, Xin Tong <xerox.time.tech@gmail.com> wrote:
>> In qemu soft TLB, there is a MMU modes. what is it and what does it do
>> ? I see target-mips, NB_MMU_MODES is defined to be 3, unfortunately,
>> there is no comments on what each one of them means in the code.
>
> This distinguishes TLB entries for kernel mode from those for user mode
> and so on. Look in target-mips/cpu.h for the MMU_MODE[012]_SUFFIX
> definitions and the cpu_mmu_index() function, which should tell you what
> MIPS in particular uses them for.
>
> -- PMM