From: Jim Shu <jim.shu@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
chigot@adacore.com
Subject: Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC
Date: Tue, 11 Oct 2022 13:16:54 +0800 [thread overview]
Message-ID: <CALw707rXdhbeYiWQTb-fGDR56CfnzbY7eoacLS8hKvgded+Kew@mail.gmail.com> (raw)
In-Reply-To: <20221003041440.2320-1-jim.shu@sifive.com>
Gentle ping.
It's a patch for fix and spec alignment of PLIC.
On Mon, Oct 3, 2022 at 12:14 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
> * fix opposite of power-of-2 max priority checking expression.
>
> v2:
> * change interrupt priority register to WARL field.
>
> Jim Shu (2):
> hw/intc: sifive_plic: fix hard-coded max priority level
> hw/intc: sifive_plic: change interrupt priority register to WARL field
>
> hw/intc/sifive_plic.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-10-11 5:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-03 4:14 [PATCH v3 0/2] Enhance maximum priority support of PLIC Jim Shu
2022-10-03 4:14 ` [PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level Jim Shu
2022-10-11 5:47 ` Alistair Francis
2022-10-03 4:14 ` [PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field Jim Shu
2022-10-03 7:07 ` Clément Chigot
2022-10-11 5:50 ` Alistair Francis
2022-10-11 5:16 ` Jim Shu [this message]
2022-10-11 22:47 ` [PATCH v3 0/2] Enhance maximum priority support of PLIC Alistair Francis
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