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From: Jim Shu <jim.shu@sifive.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Zhao Liu" <zhao1.liu@intel.com>, "Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Helge Deller" <deller@gmx.de>, "Song Gao" <gaosong@loongson.cn>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Aleksandar Rikalo" <arikalo@gmail.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"Nicholas Piggin" <npiggin@gmail.com>,
	"Ilya Leoshkevich" <iii@linux.ibm.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	"open list:PowerPC TCG CPUs" <qemu-ppc@nongnu.org>,
	"open list:S390 TCG CPUs" <qemu-s390x@nongnu.org>
Subject: Re: [PATCH v2 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs
Date: Wed, 8 Oct 2025 13:54:13 +0800	[thread overview]
Message-ID: <CALw707rstv76_oESKHzbeuPakSesWNBXogQoCJN4pHMj_wz7eg@mail.gmail.com> (raw)
In-Reply-To: <e7616702-8a7b-4617-8433-236a1086bdf9@ventanamicro.com>

Hi Daniel,

Both '_reserved1' and '_reserved2' fields are only for padding
MemTxAttrs struct to be 8-byte [1], so I remove a 1-byte reserved
field when adding 'world_id' field to it.
Is it ok for you? Or you think it is better to separate them.


[1]
commit 5014e33b1e00d330f13df33c09a3932ac88f8d94
Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel.com

Thanks!

On Sat, Aug 9, 2025 at 8:34 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 4/17/25 7:52 AM, Jim Shu wrote:
> > RISC-V WorldGuard will add 5-bit world_id (WID) to the each memory
> > transaction on the bus. The wgChecker in front of RAM or peripherals
> > MMIO could do the access control based on the WID. It is similar to ARM
> > TrustZone NS bit, but the WID is 5-bit.
> >
> > The common implementation of WID is AXI4 AxUSER signal.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > ---
> >   include/exec/memattrs.h | 8 ++++++--
> >   1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> > index 8db1d30464..7a6866fa41 100644
> > --- a/include/exec/memattrs.h
> > +++ b/include/exec/memattrs.h
> > @@ -54,6 +54,11 @@ typedef struct MemTxAttrs {
> >        */
> >       unsigned int pid:8;
> >
> > +    /*
> > +     * RISC-V WorldGuard: the 5-bit WID field of memory access.
> > +     */
> > +    unsigned int world_id:5;
> > +
> >       /*
> >        * Bus masters which don't specify any attributes will get this
> >        * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
> > @@ -63,8 +68,7 @@ typedef struct MemTxAttrs {
> >        */
> >       bool unspecified;
> >
> > -    uint8_t _reserved1;
> > -    uint16_t _reserved2;
> > +    uint16_t _reserved1;
>
> Is 'reserved2' unused? Not sure why you ended up removing it in this patch.
>
> If it's really unused it's ok to remove it but this should be done in separate.
>
>
> Thanks,
>
> Daniel
>
>
> >   } MemTxAttrs;
> >
> >   QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8);
>


  reply	other threads:[~2025-10-08  5:55 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-17 10:52 [PATCH v2 00/18] Implements RISC-V WorldGuard extension v0.4 Jim Shu
2025-04-17 10:52 ` [PATCH v2 01/18] accel/tcg: Store section pointer in CPUTLBEntryFull Jim Shu
2025-04-17 10:52 ` [PATCH v2 02/18] system/physmem: Remove the assertion of page-aligned section number Jim Shu
2025-04-17 10:52 ` [PATCH v2 03/18] accel/tcg: memory access from CPU will pass access_type to IOMMU Jim Shu
2025-04-17 10:52 ` [PATCH v2 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs Jim Shu
2025-08-09 12:34   ` Daniel Henrique Barboza
2025-10-08  5:54     ` Jim Shu [this message]
2025-10-12 17:27       ` Daniel Henrique Barboza
2025-10-16  3:33         ` Jim Shu
2025-04-17 10:52 ` [PATCH v2 05/18] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config Jim Shu
2025-08-09 12:37   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 06/18] target/riscv: Add CPU options of WorldGuard CPU extension Jim Shu
2025-08-09 12:47   ` Daniel Henrique Barboza
2025-10-08  7:22     ` Jim Shu
2025-04-17 10:52 ` [PATCH v2 07/18] target/riscv: Add hard-coded CPU state of WG extension Jim Shu
2025-04-17 10:52 ` [PATCH v2 08/18] target/riscv: Add defines for WorldGuard CSRs Jim Shu
2025-08-09 12:49   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 09/18] target/riscv: Allow global WG config to set WG CPU callbacks Jim Shu
2025-08-09 12:50   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 10/18] target/riscv: Implement WorldGuard CSRs Jim Shu
2025-08-09 12:54   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 11/18] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Jim Shu
2025-04-17 10:52 ` [PATCH v2 12/18] target/riscv: Expose CPU options of WorldGuard Jim Shu
2025-08-09 12:55   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 13/18] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Jim Shu
2025-08-09 13:07   ` Daniel Henrique Barboza
2025-08-13  3:07     ` Chao Liu
2025-10-08  6:19       ` Jim Shu
2025-04-17 10:52 ` [PATCH v2 14/18] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker Jim Shu
2025-08-09 16:39   ` Daniel Henrique Barboza
2025-10-08  7:23     ` Jim Shu
2025-04-17 10:52 ` [PATCH v2 15/18] hw/misc: riscv_wgchecker: Implement wgchecker slot registers Jim Shu
2025-08-09 16:42   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 16/18] hw/misc: riscv_wgchecker: Implement correct block-access behavior Jim Shu
2025-04-17 10:52 ` [PATCH v2 17/18] hw/misc: riscv_wgchecker: Check the slot settings in translate Jim Shu
2025-08-09 16:43   ` Daniel Henrique Barboza
2025-04-17 10:52 ` [PATCH v2 18/18] hw/riscv: virt: Add WorldGuard support Jim Shu
2025-08-09 16:53   ` Daniel Henrique Barboza
2025-10-08  7:23     ` Jim Shu
2025-08-09 17:00 ` [PATCH v2 00/18] Implements RISC-V WorldGuard extension v0.4 Daniel Henrique Barboza

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