From: Ian Jiang <ianjiang.ict@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing
Date: Mon, 27 Jan 2020 22:17:35 +0800 [thread overview]
Message-ID: <CAMAD20k20TaR+SQrj4X_m7qW=aiwrjy_aiWwsXuKBoQ54a58hg@mail.gmail.com> (raw)
In-Reply-To: <ddd76565-4139-35e6-a23d-9e2c13fc613c@linaro.org>
Got it.
As the first step, I just summit a new patch:
[PATCH] riscv: Add helper to make NaN-boxing for FP register
I'd like to carry out other fixes after this patch is reviewed.
Richard Henderson <richard.henderson@linaro.org> 于2020年1月24日周五 上午2:53写道：
>
> On 1/22/20 6:05 PM, Ian Jiang wrote:
> > But I am not clear where to call this new helper gen_nanbox_fpr(). Is
> > there a position that could affect all floating-point instructions? So
> > that we don't have to modify so many translating functions. Please
> > give more details.
>
> No, this will have to be called for each instruction individually.
>
> That said, all of the insns that use helper functions, such as fsqrt_s, should
> be doing the nan-boxing within the helper function. Thus you'll want a
> different helper function for use within fpu_helper.c.
>
>
> r~
prev parent reply other threads:[~2020-01-27 14:18 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-22 7:24 [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing Ian Jiang
2020-01-22 8:53 ` Richard Henderson
2020-01-22 9:53 ` Ian Jiang
2020-01-22 17:10 ` Richard Henderson
2020-01-23 0:48 ` Ian Jiang
2020-01-23 3:07 ` Richard Henderson
2020-01-23 4:05 ` Ian Jiang
2020-01-23 18:52 ` Richard Henderson
2020-01-27 14:17 ` Ian Jiang [this message]
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