From: Ian Jiang <ianjiang.ict@gmail.com>
To: qemu-devel@nongnu.org
Subject: riscv: How to get more CSR information in debug trace?
Date: Fri, 17 Jan 2020 21:32:55 +0800 [thread overview]
Message-ID: <CAMAD20nGNi3N=Nj0x_ifUkH0Hb465eG77w6VG-vPLb1u1mPCsw@mail.gmail.com> (raw)
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The following registers are given in QEMU debug trace with "-d cpu"
parameter.
pc 0000000000001000
mhartid 0000000000000000
mstatus 0000000000000000
mip 0x0
mie 0000000000000000
mideleg 0000000000000000
medeleg 0000000000000000
mtvec 0000000000000000
mepc 0000000000000000
mcause 0000000000000000
I want more information of other CSRs, such as sstatus, misa, pmpconfig0.
How to get debug trace on all CSRs defined in RISC-V specification?
Thanks!
--
Ian Jiang
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next reply other threads:[~2020-01-17 13:36 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-17 13:32 Ian Jiang [this message]
2020-01-20 23:06 ` riscv: How to get more CSR information in debug trace? Alistair Francis
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