* riscv: How to get more CSR information in debug trace?
@ 2020-01-17 13:32 Ian Jiang
2020-01-20 23:06 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Ian Jiang @ 2020-01-17 13:32 UTC (permalink / raw)
To: qemu-devel
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The following registers are given in QEMU debug trace with "-d cpu"
parameter.
pc 0000000000001000
mhartid 0000000000000000
mstatus 0000000000000000
mip 0x0
mie 0000000000000000
mideleg 0000000000000000
medeleg 0000000000000000
mtvec 0000000000000000
mepc 0000000000000000
mcause 0000000000000000
I want more information of other CSRs, such as sstatus, misa, pmpconfig0.
How to get debug trace on all CSRs defined in RISC-V specification?
Thanks!
--
Ian Jiang
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: riscv: How to get more CSR information in debug trace?
2020-01-17 13:32 riscv: How to get more CSR information in debug trace? Ian Jiang
@ 2020-01-20 23:06 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2020-01-20 23:06 UTC (permalink / raw)
To: Ian Jiang; +Cc: qemu-devel@nongnu.org Developers
On Fri, Jan 17, 2020 at 11:36 PM Ian Jiang <ianjiang.ict@gmail.com> wrote:
>
> The following registers are given in QEMU debug trace with "-d cpu" parameter.
> pc 0000000000001000
> mhartid 0000000000000000
> mstatus 0000000000000000
> mip 0x0
> mie 0000000000000000
> mideleg 0000000000000000
> medeleg 0000000000000000
> mtvec 0000000000000000
> mepc 0000000000000000
> mcause 0000000000000000
>
> I want more information of other CSRs, such as sstatus, misa, pmpconfig0.
> How to get debug trace on all CSRs defined in RISC-V specification?
You can use the `info registers` command from the QEMU monitor.
Otherwise you could edit the source code to trace the registers you
are interested in.
The problem is there are so many CSRs we can't print them all.
Alistair
> Thanks!
>
> --
> Ian Jiang
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