Re: [RFC PATCH v2 2/4] hw/i386/acpi-build: Add ACPI PCI hot-plug methods to q35

[Julia Suvorova <jusual@redhat.com>]

On Fri, Aug 21, 2020 at 2:08 PM Igor Mammedov <imammedo@redhat.com> wrote:
>
> On Tue, 18 Aug 2020 23:52:25 +0200
> Julia Suvorova <jusual@redhat.com> wrote:
>
> > Implement notifications and gpe to support q35 ACPI PCI hot-plug.
> > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.
>
> in addition to comment from Philippe
>
>
> >
> > Signed-off-by: Julia Suvorova <jusual@redhat.com>
> > ---
> >  include/hw/acpi/pcihp.h |  3 ++-
> >  hw/acpi/pcihp.c         | 10 ++++++----
> >  hw/acpi/piix4.c         |  2 +-
> >  hw/i386/acpi-build.c    | 25 ++++++++++++++-----------
> >  4 files changed, 23 insertions(+), 17 deletions(-)
> >
> > diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
> > index 8bc4a4c01d..1e9d246f57 100644
> > --- a/include/hw/acpi/pcihp.h
> > +++ b/include/hw/acpi/pcihp.h
> > @@ -54,7 +54,8 @@ typedef struct AcpiPciHpState {
> >  } AcpiPciHpState;
> >
> >  void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
> > -                     MemoryRegion *address_space_io, bool bridges_enabled);
> > +                     MemoryRegion *address_space_io, bool bridges_enabled,
> > +                     bool is_piix4);
> >
> >  void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,
> >                                     DeviceState *dev, Error **errp);
> > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
> > index 9e31ab2da4..9a35ed6c83 100644
> > --- a/hw/acpi/pcihp.c
> > +++ b/hw/acpi/pcihp.c
> > @@ -38,7 +38,8 @@
> >  #include "qom/qom-qobject.h"
> >  #include "trace.h"
> >
> > -#define ACPI_PCIHP_ADDR 0xae00
> > +#define ACPI_PCIHP_ADDR_PIIX4 0xae00
> > +#define ACPI_PCIHP_ADDR_Q35 0x0cc4
> >  #define ACPI_PCIHP_SIZE 0x0014
> >  #define PCI_UP_BASE 0x0000
> >  #define PCI_DOWN_BASE 0x0004
> > @@ -359,12 +360,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
> >  };
> >
> >  void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
> > -                     MemoryRegion *address_space_io, bool bridges_enabled)
> > +                     MemoryRegion *address_space_io, bool bridges_enabled,
> > +                     bool is_piix4)
> >  {
> >      s->io_len = ACPI_PCIHP_SIZE;
> > -    s->io_base = ACPI_PCIHP_ADDR;
> > +    s->io_base = is_piix4 ? ACPI_PCIHP_ADDR_PIIX4 : ACPI_PCIHP_ADDR_Q35;
> >
> > -    s->root= root_bus;
> > +    s->root = root_bus;
> >      s->legacy_piix = !bridges_enabled;
> >
> >      memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index cdfa0e2998..1f27bfbd06 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -596,7 +596,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
> >      memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
> >
> >      acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
> > -                    s->use_acpi_hotplug_bridge);
> > +                    s->use_acpi_hotplug_bridge, true);
> >
> >      s->cpu_hotplug_legacy = true;
> >      object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index b7bcbbbb2a..f3cd52bd06 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -201,10 +201,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
> >          /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
> >          pm->fadt.rev = 1;
> >          pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
> > -        pm->pcihp_io_base =
> > -            object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
> > -        pm->pcihp_io_len =
> > -            object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
> >      }
> >      if (lpc) {
> >          struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
> > @@ -214,6 +210,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
> >          pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
> >          pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
> >      }
> > +    pm->pcihp_io_base =
> > +        object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
> > +    pm->pcihp_io_len =
> > +        object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
> >
> >      /* The above need not be conditional on machine type because the reset port
> >       * happens to be the same on PIIX (pc) and ICH9 (q35). */
> > @@ -472,7 +472,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
> >          QLIST_FOREACH(sec, &bus->child, sibling) {
> >              int32_t devfn = sec->parent_dev->devfn;
> >
> > -            if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
> > +            if (pci_bus_is_root(sec)) {
> Does pcie bus on hostbridge fall into pci_bus_is_express() categiry or not?

I don't understand why it's there in the first place.
pci_bus_is_root() check is for pxb, but pci_bus_is_express() is
useless because everything is under 'if (pcihp_bridge_en) {', which
means that no pcie bus will get there (before this patch).

> >                  continue;
> >              }
> >
> > @@ -1368,7 +1368,7 @@ static void build_piix4_isa_bridge(Aml *table)
> >      aml_append(table, scope);
> >  }
> >
> > -static void build_piix4_pci_hotplug(Aml *table)
> > +static void build_i386_pci_hotplug(Aml *table, uint64_t pcihp_addr)
> >  {
> >      Aml *scope;
> >      Aml *field;
> > @@ -1377,20 +1377,22 @@ static void build_piix4_pci_hotplug(Aml *table)
> >      scope =  aml_scope("_SB.PCI0");
> >
> >      aml_append(scope,
> > -        aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
> > +        aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
> >      field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
> >      aml_append(field, aml_named_field("PCIU", 32));
> >      aml_append(field, aml_named_field("PCID", 32));
> >      aml_append(scope, field);
> >
> >      aml_append(scope,
> > -        aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
> > +    aml_operation_region("SEJ", AML_SYSTEM_IO,
> > +                         aml_int(pcihp_addr + 0x08), 0x04));
>                                                  ^^^^
> how about turning this offset into macro?
>
> >      field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
> >      aml_append(field, aml_named_field("B0EJ", 32));
> >      aml_append(scope, field);
> >
> >      aml_append(scope,
> > -        aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
> > +        aml_operation_region("BNMR", AML_SYSTEM_IO,
> > +                             aml_int(pcihp_addr + 0x10), 0x04));
> ditto
>
> >      field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
> >      aml_append(field, aml_named_field("BNUM", 32));
> >      aml_append(scope, field);
> > @@ -1504,7 +1506,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >          build_hpet_aml(dsdt);
> >          build_piix4_isa_bridge(dsdt);
> >          build_isa_devices_aml(dsdt);
> > -        build_piix4_pci_hotplug(dsdt);
> >          build_piix4_pci0_int(dsdt);
> >      } else {
> >          sb_scope = aml_scope("_SB");
> > @@ -1526,6 +1527,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >          }
> >      }
> >
> > +    build_i386_pci_hotplug(dsdt, pm->pcihp_io_base);
> > +
> >      if (pcmc->legacy_cpu_hotplug) {
> >          build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
> >      } else {
> > @@ -1546,7 +1549,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> >      {
> >          aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
> >
> > -        if (misc->is_piix4) {
> > +        if (misc->is_piix4 || pm->pcihp_bridge_en) {
> >              method = aml_method("_E01", 0, AML_NOTSERIALIZED);
> >              aml_append(method,
> >                  aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
>