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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=yongxuan.wang@sifive.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, On Fri, Aug 9, 2024 at 5:40=E2=80=AFAM Daniel Henrique Barboza wrote: > > Ccing Anup > > On 8/8/24 5:20 AM, Yong-Xuan Wang wrote: > > In the section "4.7 Precise effects on interrupt-pending bits" > > of the RISC-V AIA specification defines that: > > > > If the source mode is Level1 or Level0 and the interrupt domain > > is configured in MSI delivery mode (domaincfg.DM =3D 1): > > The pending bit is cleared whenever the rectified input value is > > low, when the interrupt is forwarded by MSI, or by a relevant > > write to an in clrip register or to clripnum. > > > > Update the riscv_aplic_set_pending() to match the spec. > > > > This would need a > > Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation = for APLIC MSI-mode") > I will add it into next version. Thank you! > > Signed-off-by: Yong-Xuan Wang > > --- > > hw/intc/riscv_aplic.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > > index c1748c2d17d1..45d8b4089229 100644 > > --- a/hw/intc/riscv_aplic.c > > +++ b/hw/intc/riscv_aplic.c > > @@ -247,7 +247,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState= *aplic, > > > > if ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_HIGH) || > > (sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW)) { > > - if (!aplic->msimode || (aplic->msimode && !pending)) { > > + if (!aplic->msimode) { > > The change you're doing here seems sensible to me but I'd rather have Anu= p take > a look to see if this somehow undo what was made here in commit bf31cf06. > > In particular w.r.t this paragraph from section 4.9.2 of AIA: > > "A second option is for the interrupt service routine to write the > APLIC=E2=80=99s source identity number for the interrupt to the domain=E2= =80=99s > setipnum register just before exiting. This will cause the interrupt=E2= =80=99s > pending bit to be set to one again if the source is still asserting > an interrupt, but not if the source is not asserting an interrupt." > I think that this patch won't affect setipnum. For the setipnum case, the pending value would be true. And it is handled by the 2 if conditions below. Regards, Yong-Xuan > > Thanks, > > Daniel > > > > return; > > } > > if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&