From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
frank.chang@sifive.com, jim.shu@sifive.com,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 4/8] target/riscv: add helper to get CSR name
Date: Mon, 24 Feb 2025 15:56:42 +0800 [thread overview]
Message-ID: <CAMWQL2ihmaRfkqDtr9Z6eeh=fCMZb1TqSk_h0AoeYxU1g21_sQ@mail.gmail.com> (raw)
In-Reply-To: <20250217-d6ff55e1f04b68643ae8295e@orel>
Hi Andrew,
On Mon, Feb 17, 2025 at 10:01 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote:
> > Add a helper function to get CSR name from CSR number.
> >
> > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> > ---
> > target/riscv/cpu.h | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 616c3bdc1c24..133d1852ee1e 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -920,8 +920,12 @@ extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
> > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
> > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
> >
> > -void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> > +static inline const char *riscv_get_csr_name(int csr_no)
> > +{
> > + return csr_ops[csr_no & (CSR_TABLE_SIZE - 1)].name;
>
> Shouldn't we assert csr_no is correct rather than silently
> truncate it?
ok. I would add some assertions in this function.
Regards,
Yong-Xuan
>
> Thanks,
> drew
>
> > +}
> >
> > +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> > target_ulong riscv_new_csr_seed(target_ulong new_value,
> > target_ulong write_mask);
> >
> > --
> > 2.17.1
> >
> >
next prev parent reply other threads:[~2025-02-24 7:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 8:17 [PATCH 0/8] riscv: AIA: kernel-irqchip=off support Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 4/8] target/riscv: add helper to get CSR name Yong-Xuan Wang
2025-02-17 14:01 ` Andrew Jones
2025-02-24 7:56 ` Yong-Xuan Wang [this message]
2025-02-17 8:17 ` [PATCH 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic Yong-Xuan Wang
2025-02-17 14:07 ` Andrew Jones
2025-02-19 11:26 ` Yong-Xuan Wang
2025-02-17 8:17 ` [PATCH 8/8] docs: update the description about RISC-V AIA Yong-Xuan Wang
2025-02-18 15:53 ` [PATCH 0/8] riscv: AIA: kernel-irqchip=off support Kashyap Chamarthy
2025-02-24 7:17 ` Yong-Xuan Wang
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