From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TELlx-0002KV-Ob for qemu-devel@nongnu.org; Wed, 19 Sep 2012 11:01:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TELlr-0005K2-Lr for qemu-devel@nongnu.org; Wed, 19 Sep 2012 11:01:05 -0400 Received: from mail-oa0-f45.google.com ([209.85.219.45]:49807) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TELlr-0005Jy-Gh for qemu-devel@nongnu.org; Wed, 19 Sep 2012 11:00:59 -0400 Received: by oagn12 with SMTP id n12so1059040oag.4 for ; Wed, 19 Sep 2012 08:00:58 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: Date: Wed, 19 Sep 2012 19:00:58 +0400 Message-ID: From: Max Filippov Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] Shifts, ppc[64], xtensa List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: malc Cc: qemu-devel@nongnu.org, Richard Henderson On Wed, Sep 19, 2012 at 4:49 PM, malc wrote: > On Wed, 19 Sep 2012, Max Filippov wrote: > >> On Tue, Sep 18, 2012 at 11:52 PM, malc wrote: >> > >> > Looks like PPC/PPC64 is also hit by shift issues, on top of that xtensa >> >> malc, could you please expand a little bit what are these shift issues? >> (sounds like a modern trend, I must have missed something) >> > > Just audit op_opt output of extensa on 32bit host for shr_i32, i'm getting > things like: > > OP after optimization and liveness analysis: > movi_i32 tmp0,$0xd00793f4 > movi_i32 tmp1,$0x1 > movi_i32 tmp2,$0x1 > movi_i32 tmp3,$advance_ccount > call tmp3,$0x0,$0,env,tmp2 > movi_i32 tmp2,$window_check > call tmp2,$0x0,$0,env,tmp0,tmp1 > movi_i32 tmp0,$0x1 > add_i32 ar4,ar4,tmp0 > movi_i32 tmp1,$0xd00793f6 > movi_i32 tmp2,$0x3 > movi_i32 tmp3,$0x1 > movi_i32 tmp4,$advance_ccount > call tmp4,$0x0,$0,env,tmp3 > movi_i32 tmp3,$window_check > call tmp3,$0x0,$0,env,tmp1,tmp2 > mov_i32 tmp0,ar4 > qemu_ld8u ar12,tmp0,$0x0 > movi_i32 tmp0,$0xffffffe0 > add_i32 ar9,ar12,tmp0 > <<< > movi_i32 tmp1,$0x40 > shr_i32 tmp0,ar9,tmp1 > <<< Thanks for the report, this stands for extui, should be fixed with the following: -- >8 -- From: Max Filippov Date: Wed, 19 Sep 2012 18:58:30 +0400 Subject: [PATCH] target-xtensa: fix extui shift amount extui opcode only uses lowermost op1 bit for sa4. Reported-by: malc Signed-off-by: Max Filippov --- target-xtensa/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1900bd5..63b37b3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1778,7 +1778,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: gen_window_check2(dc, RRR_R, RRR_T); { - int shiftimm = RRR_S | (OP1 << 4); + int shiftimm = RRR_S | ((OP1 & 1) << 4); int maskimm = (1 << (OP2 + 1)) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); -- 1.7.5.4