From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhNop-0006U0-NJ for qemu-devel@nongnu.org; Wed, 30 Sep 2015 16:17:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhNoo-0001Gx-Ly for qemu-devel@nongnu.org; Wed, 30 Sep 2015 16:17:39 -0400 Received: from mail-oi0-x231.google.com ([2607:f8b0:4003:c06::231]:34046) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhNoo-0001Gt-Hz for qemu-devel@nongnu.org; Wed, 30 Sep 2015 16:17:38 -0400 Received: by oiev17 with SMTP id v17so29147000oie.1 for ; Wed, 30 Sep 2015 13:17:38 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1443374214-27149-1-git-send-email-jcmvbkbc@gmail.com> <1443374214-27149-4-git-send-email-jcmvbkbc@gmail.com> Date: Wed, 30 Sep 2015 23:17:37 +0300 Message-ID: From: Max Filippov Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 3/3] target-xtensa: xtfpga: support noMMU cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Peter Crosthwaite , =?UTF-8?Q?Andreas_F=C3=A4rber?= , "qemu-devel@nongnu.org Developers" On Tue, Sep 29, 2015 at 11:42 PM, Peter Maydell wrote: > On 29 September 2015 at 11:34, Max Filippov wrote: >> Changing address space layout according to CPU type is what happens >> in actual hardware. There are no user-controllable settings that would >> allow mismatching address space layout and CPU type on XTFPGA >> boards. There's also no SoC level mentioned in the developer guides >> for the corresponding boards. So I'm not sure what you're proposing to do. > > I think this should clearly be different machine models > (possibly implemented using different SoC models). There are already 4 different machine models, lx60, lx200, ml605 and kc705, these are real boards for which bitstreams can be created. > This isn't a > CPU-dependent thing at all, it's just your dev tools are hiding > "change the devices and other board/soc level things" behind a > CPU-type dropdown, which it can get away with because the whole > implementation is in a single FPGA. Why duplicating each machine and then only allowing each CPU to be used with only one variant of each machine? It doesn't match what users do with boards and bitstreams, at all. -- Thanks. -- Max