From: Titus Rwantare <titusr@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Yubin Zou <yubinz@google.com>,
qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Tyrone Ting <kfting@nuvoton.com>, Hao Wu <wuhaotsh@google.com>,
qemu-arm@nongnu.org
Subject: Re: [PATCH 2/7] hw/pci-host: add basic Nuvoton PCIe window support
Date: Thu, 25 Sep 2025 12:39:24 -0700 [thread overview]
Message-ID: <CAMvPwGo-PpapVgYG9RRdtzEOzFzgn1++f-uTHyyDHzfjyNTPfg@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA8QAj54xxTfk087=8dERGiM28Bz2mw9eVtMd6qNOd7aYw@mail.gmail.com>
On Thu, 25 Sept 2025 at 09:38, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 9 Sept 2025 at 23:11, Yubin Zou <yubinz@google.com> wrote:
> >
> > From: Titus Rwantare <titusr@google.com>
> >
> > Adds the windowing registers without address translation
> >
> > Signed-off-by: Titus Rwantare <titusr@google.com>
> > ---
> > hw/pci-host/npcm_pcierc.c | 223 +++++++++++++++++++++++++++++++++++++-
> > include/hw/pci-host/npcm_pcierc.h | 77 ++++++++++++-
> > 2 files changed, 297 insertions(+), 3 deletions(-)
> >
> > diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c
> > index 3afe92e264f6ce4312e94f05b5e908840008df64..bffdec71acaba6562856b3bdd8aec07c3c153323 100644
> > --- a/hw/pci-host/npcm_pcierc.c
> > +++ b/hw/pci-host/npcm_pcierc.c
> > @@ -16,6 +16,193 @@
> > #include "qom/object.h"
> > #include "trace.h"
> >
> > +/* Map enabled windows to a memory subregion */
> > +static void npcm_pcierc_map_enabled(NPCMPCIERCState *s, NPCMPCIEWindow *w)
> > +{
> > + MemoryRegion *system = get_system_memory();
>
> > + /* TODO: set subregion to target translation address */
> > + /* add subregion starting at the window source address */
> > + if (!memory_region_is_mapped(&w->mem)) {
> > + memory_region_init(&w->mem, OBJECT(s), name, size);
> > + memory_region_add_subregion(system, bar, &w->mem);
> > + }
>
> This looks weird. Generally devices should not map themselves
> into the system address space, although some of our older
> pci-host devices do for historical reasons. Should we
> be modelling this some other way?
>
> thanks
> -- PMM
I can update this. What devices are doing it the new way?
-Titus
next prev parent reply other threads:[~2025-09-25 19:41 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-09 22:10 [PATCH 0/7] Introduce PCIE Root Complex on Nuvoton npcm8xx and npcm7xx Yubin Zou
2025-09-09 22:10 ` [PATCH 1/7] hw/pci-host: implement Nuvoton PCIE Root Complex stub Yubin Zou
2025-09-30 1:33 ` KFTING
2025-09-09 22:10 ` [PATCH 2/7] hw/pci-host: add basic Nuvoton PCIe window support Yubin Zou
2025-09-25 16:38 ` Peter Maydell
2025-09-25 19:39 ` Titus Rwantare [this message]
2025-09-26 9:07 ` Peter Maydell
2025-09-30 1:34 ` KFTING
2025-09-09 22:10 ` [PATCH 3/7] hw/arm: attach PCIe root complex to npmcm8xx Yubin Zou
2025-09-30 1:35 ` KFTING
2025-09-09 22:10 ` [PATCH 4/7] hw/pci-host: add Nuvoton PCIe root port Yubin Zou
2025-09-25 16:42 ` Peter Maydell
2025-09-30 1:34 ` KFTING
2025-09-09 22:11 ` [PATCH 5/7] hw/pci-host: enable MSI on npcm PCIe root complex Yubin Zou
2025-09-30 1:36 ` KFTING
2025-09-09 22:11 ` [PATCH 6/7] hw/pci-host: rework Nuvoton PCIe windowing and memory regions Yubin Zou
2025-09-25 16:40 ` Peter Maydell
2025-09-30 1:34 ` KFTING
2025-09-09 22:11 ` [PATCH 7/7] hw/arm: Add PCIERC to NPCM7xx SoC Yubin Zou
2025-09-30 1:36 ` KFTING
2025-09-25 16:43 ` [PATCH 0/7] Introduce PCIE Root Complex on Nuvoton npcm8xx and npcm7xx Peter Maydell
2025-09-30 1:32 ` KFTING
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