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Thu, 25 Sep 2025 12:40:01 -0700 (PDT) MIME-Version: 1.0 References: <20250909-pcie-root-upstream-v1-0-d85883b2688d@google.com> <20250909-pcie-root-upstream-v1-2-d85883b2688d@google.com> In-Reply-To: From: Titus Rwantare Date: Thu, 25 Sep 2025 12:39:24 -0700 X-Gm-Features: AS18NWBTtowT4M59ZFcVd2Lw5bbNT0R3_Fheh61VDmq6C-fwUa9w9RvuAL0bYaE Message-ID: Subject: Re: [PATCH 2/7] hw/pci-host: add basic Nuvoton PCIe window support To: Peter Maydell Cc: Yubin Zou , qemu-devel@nongnu.org, Paolo Bonzini , Tyrone Ting , Hao Wu , qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=titusr@google.com; helo=mail-lf1-x134.google.com X-Spam_score_int: -96 X-Spam_score: -9.7 X-Spam_bar: --------- X-Spam_report: (-9.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 25 Sept 2025 at 09:38, Peter Maydell wrote: > > On Tue, 9 Sept 2025 at 23:11, Yubin Zou wrote: > > > > From: Titus Rwantare > > > > Adds the windowing registers without address translation > > > > Signed-off-by: Titus Rwantare > > --- > > hw/pci-host/npcm_pcierc.c | 223 +++++++++++++++++++++++++++++++++++++- > > include/hw/pci-host/npcm_pcierc.h | 77 ++++++++++++- > > 2 files changed, 297 insertions(+), 3 deletions(-) > > > > diff --git a/hw/pci-host/npcm_pcierc.c b/hw/pci-host/npcm_pcierc.c > > index 3afe92e264f6ce4312e94f05b5e908840008df64..bffdec71acaba6562856b3bdd8aec07c3c153323 100644 > > --- a/hw/pci-host/npcm_pcierc.c > > +++ b/hw/pci-host/npcm_pcierc.c > > @@ -16,6 +16,193 @@ > > #include "qom/object.h" > > #include "trace.h" > > > > +/* Map enabled windows to a memory subregion */ > > +static void npcm_pcierc_map_enabled(NPCMPCIERCState *s, NPCMPCIEWindow *w) > > +{ > > + MemoryRegion *system = get_system_memory(); > > > + /* TODO: set subregion to target translation address */ > > + /* add subregion starting at the window source address */ > > + if (!memory_region_is_mapped(&w->mem)) { > > + memory_region_init(&w->mem, OBJECT(s), name, size); > > + memory_region_add_subregion(system, bar, &w->mem); > > + } > > This looks weird. Generally devices should not map themselves > into the system address space, although some of our older > pci-host devices do for historical reasons. Should we > be modelling this some other way? > > thanks > -- PMM I can update this. What devices are doing it the new way? -Titus