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bh=mwg1X7miNdObgg0WMJUaSU7st35j6DWbfGZeKCpy0Lw=; b=av4FMNWQJ8SvbL6+fF+cFiDWNUdLybtMJZBZ37D2VKRzt+h8s8Pyy+LVlPaumRVz16 P6u5qotsw9AtYh1WyIpKfvQJ1bWrsHBAvyQnwuNcya/STasbtSFueF0SJQYVHsRGwxOW QBAr9ux8gtPk+nqZrPYR2Rlp7LyOCG/9NT73TNVuZJDdPtbpyc7hun80NJYNU0TVDJXi KJiafixLwmlC/lCpVCl7QXmr80PIUxUXXcbTReZQsUH2Y0DwLUhVSsbr5152gbH8Py80 tVSgkWXxXRfQR4w4piTyJUHfe/fnz25EF1dP86Zt8FROCxQzkBvCJuKL2uvkPHHe8pfi QPEA== X-Gm-Message-State: AAQBX9d2ShJ+c8YMDj+D9caxI1yIfeXhrwXzvxWUHbU3MxiKxXbn1Q3O wxKHrcH9Si2wj77YTqaIrW9z7ER0IC9a/NxIhtmIhg== X-Google-Smtp-Source: AKy350ZCuVD+jNBcwO3/e8e945Qzl8gqZ4p5L2OmvW1l5f3qdzDeP+IFNWScmmcuCgK2SVJSxICGQRkRCw/aR27/ts8= X-Received: by 2002:ad4:5948:0:b0:5e3:d150:3168 with SMTP id eo8-20020ad45948000000b005e3d1503168mr29705793qvb.18.1682529235656; Wed, 26 Apr 2023 10:13:55 -0700 (PDT) MIME-Version: 1.0 References: <20230414160202.1298242-1-mchitale@ventanamicro.com> <20230414160202.1298242-3-mchitale@ventanamicro.com> <130dce28-e116-bfca-cd94-e63c48073818@iscas.ac.cn> In-Reply-To: <130dce28-e116-bfca-cd94-e63c48073818@iscas.ac.cn> From: Mayuresh Chitale Date: Wed, 26 Apr 2023 22:43:19 +0530 Message-ID: Subject: Re: [RFC PATCH v2 2/4] target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS To: Weiwei Li Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Alistair Francis , Daniel Barboza , Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::f31; envelope-from=mchitale@ventanamicro.com; helo=mail-qv1-xf31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Apr 15, 2023 at 7:15=E2=80=AFAM Weiwei Li wr= ote: > > > On 2023/4/15 00:02, Mayuresh Chitale wrote: > > When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can > > be used to save the current state of smstateen0.FCSR check which is > > needed by the floating point translation routines. > > > > Signed-off-by: Mayuresh Chitale > > --- > > target/riscv/cpu_helper.c | 12 ++++++++++++ > > target/riscv/translate.c | 7 +++++++ > > 2 files changed, 19 insertions(+) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 433ea529b0..fd1731cc39 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -105,6 +105,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, targ= et_ulong *pc, > > flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, > > get_field(env->mstatus_hs, MSTATUS_VS)); > > } > > + /* > > + * If misa.F is 0 then the MSTATUS_HS_FS field of the tb->flags > > + * can be used to pass the current state of the smstateen.FCSR bit > > + * which must be checked for in the floating point translation rou= tines > > + */ > > + if (!riscv_has_ext(env, RVF)) { > > + if (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) { > > + flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 1); > > + } else { > > + flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 0); > > + } > > + } > > if (cpu->cfg.debug && !icount_enabled()) { > > flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger= _enabled); > > } > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > > index d0094922b6..e29bbb8b70 100644 > > --- a/target/riscv/translate.c > > +++ b/target/riscv/translate.c > > @@ -79,6 +79,7 @@ typedef struct DisasContext { > > int frm; > > RISCVMXL ol; > > bool virt_inst_excp; > > + bool smstateen_fcsr_ok; > > bool virt_enabled; > > const RISCVCPUConfig *cfg_ptr; > > bool hlsx; > > @@ -1202,6 +1203,12 @@ static void riscv_tr_init_disas_context(DisasCon= textBase *dcbase, CPUState *cs) > > ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > > ctx->zero =3D tcg_constant_tl(0); > > ctx->virt_inst_excp =3D false; > > + if (has_ext(ctx, RVF)) { > > + ctx->smstateen_fcsr_ok =3D 1; > > + } else { > > + ctx->smstateen_fcsr_ok =3D FIELD_EX32(tb_flags, TB_FLAGS, > > + MSTATUS_HS_FS); > > By the way, it may introduce new question when MSTATUS_FS and > MSTATUS_HS_FS is merged to save bits in tb_flag > > by Richerd's patchset: 20230412114333.118895-5-richard.henderson@linaro.o= rg > > such as: the check "s->mstatus_fs =3D=3D 0" in require_rvf() will be fals= e > if smstateen_fcsr_ok is true. > > However, this should be true in this case to indicate F is diabled. > > So we may need to set ctx->mstatus_fs =3D 0 here once merged with > Richerd's patchset. Yes, that is correct. > > Regards, > > Weiwei Li > > > + } > > } > > > > static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) >