* [PATCH v2] target/riscv: pmp: Ignore writes when RW=01
@ 2023-09-25 11:10 Mayuresh Chitale
2023-10-09 1:22 ` Alistair Francis
2023-10-09 1:25 ` Alistair Francis
0 siblings, 2 replies; 4+ messages in thread
From: Mayuresh Chitale @ 2023-09-25 11:10 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: Mayuresh Chitale, Alistair Francis
As per the Priv spec: "The R, W, and X fields form a collective WARL
field for which the combinations with R=0 and W=1 are reserved."
However currently such writes are not ignored as ought to be. The
combinations with RW=01 are allowed only when the Smepmp extension
is enabled and mseccfg.MML is set.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
target/riscv/pmp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5b14eb511a..8e25f145e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -120,6 +120,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (locked) {
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
} else {
+ /* If !mseccfg.MML then ignore writes with encoding RW=01 */
+ if ((val & PMP_WRITE) && !(val & PMP_READ) &&
+ !MSECCFG_MML_ISSET(env)) {
+ val &= ~(PMP_WRITE | PMP_READ);
+ }
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01
2023-09-25 11:10 [PATCH v2] target/riscv: pmp: Ignore writes when RW=01 Mayuresh Chitale
@ 2023-10-09 1:22 ` Alistair Francis
2023-10-09 1:25 ` Alistair Francis
1 sibling, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-10-09 1:22 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: qemu-riscv, qemu-devel, Alistair Francis
On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> As per the Priv spec: "The R, W, and X fields form a collective WARL
> field for which the combinations with R=0 and W=1 are reserved."
> However currently such writes are not ignored as ought to be. The
> combinations with RW=01 are allowed only when the Smepmp extension
> is enabled and mseccfg.MML is set.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 5b14eb511a..8e25f145e0 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -120,6 +120,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (locked) {
> qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
> } else {
> + /* If !mseccfg.MML then ignore writes with encoding RW=01 */
> + if ((val & PMP_WRITE) && !(val & PMP_READ) &&
> + !MSECCFG_MML_ISSET(env)) {
> + val &= ~(PMP_WRITE | PMP_READ);
> + }
> env->pmp_state.pmp[pmp_index].cfg_reg = val;
> pmp_update_rule(env, pmp_index);
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01
2023-09-25 11:10 [PATCH v2] target/riscv: pmp: Ignore writes when RW=01 Mayuresh Chitale
2023-10-09 1:22 ` Alistair Francis
@ 2023-10-09 1:25 ` Alistair Francis
2023-10-11 15:34 ` Mayuresh Chitale
1 sibling, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2023-10-09 1:25 UTC (permalink / raw)
To: Mayuresh Chitale; +Cc: qemu-riscv, qemu-devel, Alistair Francis
On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> As per the Priv spec: "The R, W, and X fields form a collective WARL
> field for which the combinations with R=0 and W=1 are reserved."
> However currently such writes are not ignored as ought to be. The
> combinations with RW=01 are allowed only when the Smepmp extension
> is enabled and mseccfg.MML is set.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
> ---
> target/riscv/pmp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 5b14eb511a..8e25f145e0 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -120,6 +120,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> if (locked) {
> qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
> } else {
> + /* If !mseccfg.MML then ignore writes with encoding RW=01 */
> + if ((val & PMP_WRITE) && !(val & PMP_READ) &&
> + !MSECCFG_MML_ISSET(env)) {
> + val &= ~(PMP_WRITE | PMP_READ);
> + }
> env->pmp_state.pmp[pmp_index].cfg_reg = val;
> pmp_update_rule(env, pmp_index);
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01
2023-10-09 1:25 ` Alistair Francis
@ 2023-10-11 15:34 ` Mayuresh Chitale
0 siblings, 0 replies; 4+ messages in thread
From: Mayuresh Chitale @ 2023-10-11 15:34 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-riscv, qemu-devel, Alistair Francis
On Mon, Oct 9, 2023 at 6:56 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale
> <mchitale@ventanamicro.com> wrote:
> >
> > As per the Priv spec: "The R, W, and X fields form a collective WARL
> > field for which the combinations with R=0 and W=1 are reserved."
> > However currently such writes are not ignored as ought to be. The
> > combinations with RW=01 are allowed only when the Smepmp extension
> > is enabled and mseccfg.MML is set.
> >
> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
>
> Do you mind rebasing this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Ok, will do that.
>
> Alistair
>
> > ---
> > target/riscv/pmp.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> > index 5b14eb511a..8e25f145e0 100644
> > --- a/target/riscv/pmp.c
> > +++ b/target/riscv/pmp.c
> > @@ -120,6 +120,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
> > if (locked) {
> > qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
> > } else {
> > + /* If !mseccfg.MML then ignore writes with encoding RW=01 */
> > + if ((val & PMP_WRITE) && !(val & PMP_READ) &&
> > + !MSECCFG_MML_ISSET(env)) {
> > + val &= ~(PMP_WRITE | PMP_READ);
> > + }
> > env->pmp_state.pmp[pmp_index].cfg_reg = val;
> > pmp_update_rule(env, pmp_index);
> > }
> > --
> > 2.34.1
> >
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-09-25 11:10 [PATCH v2] target/riscv: pmp: Ignore writes when RW=01 Mayuresh Chitale
2023-10-09 1:22 ` Alistair Francis
2023-10-09 1:25 ` Alistair Francis
2023-10-11 15:34 ` Mayuresh Chitale
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