From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Qemu-block <qemu-block@nongnu.org>,
"Bin Meng" <bin.meng@windriver.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: Re: [PATCH 05/22] hw/sd: sd: Drop sd_crc16()
Date: Sat, 2 Jan 2021 19:23:02 +0530 [thread overview]
Message-ID: <CAN8ut8Ka6qhPT8vKwebkaH3McCcNSB9k3HhDeffnrubFmFWcLA@mail.gmail.com> (raw)
In-Reply-To: <20201231113010.27108-6-bmeng.cn@gmail.com>
On Thu, Dec 31, 2020 at 5:04 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()")
> changed the 16-bit CRC to be stored at offset 64. In fact, this CRC
> calculation is completely wrong. From the original codes, it wants
> to calculate the CRC16 of the first 64 bytes of sd->data[], however
> passing 64 as the `width` to sd_crc16() actually counts 256 bytes
> starting from the `message` for the CRC16 calculation, which is not
> what we want.
>
> Besides that, it seems exisitng sd_crc16() algorithm does not match
> the SD spec, which says CRC16 is the CCITT one but the calculation
> does not produce expected result. It turns out the CRC16 was never
> transfered outside the sd core, as in sd_read_byte() we see:
>
> if (sd->data_offset >= 64)
> sd->state = sd_transfer_state;
>
> Given above reaons, let's drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/sd/sd.c | 18 ------------------
> 1 file changed, 18 deletions(-)
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
next prev parent reply other threads:[~2021-01-02 14:29 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-31 11:29 [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support Bin Meng
2020-12-31 11:29 ` [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support Bin Meng
2021-01-04 16:00 ` Francisco Iglesias
2021-01-04 23:30 ` Bin Meng
2020-12-31 11:29 ` [PATCH 02/22] hw/block: m25p80: Add various ISSI flash information Bin Meng
2021-01-05 21:16 ` Alistair Francis
2020-12-31 11:29 ` [PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence Bin Meng
2021-01-02 13:49 ` Pragnesh Patel
2020-12-31 11:29 ` [PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode Bin Meng
2021-01-02 13:50 ` Pragnesh Patel
2020-12-31 11:29 ` [PATCH 05/22] hw/sd: sd: Drop sd_crc16() Bin Meng
2021-01-02 13:53 ` Pragnesh Patel [this message]
2021-01-14 11:51 ` Philippe Mathieu-Daudé
2020-12-31 11:29 ` [PATCH 06/22] util: Add CRC16 (CCITT) calculation routines Bin Meng
2021-01-14 20:20 ` Alistair Francis
2020-12-31 11:29 ` [PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16 Bin Meng
2021-01-13 16:54 ` Alistair Francis
2020-12-31 11:29 ` [PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18) Bin Meng
2021-01-13 16:59 ` Alistair Francis
2020-12-31 11:29 ` [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer Bin Meng
2021-01-13 17:00 ` Alistair Francis
2021-01-14 11:40 ` Philippe Mathieu-Daudé
2020-12-31 11:29 ` [PATCH 10/22] hw/sd: sd: Remove duplicated codes in single/multiple block read/write Bin Meng
2021-01-13 17:02 ` Alistair Francis
2020-12-31 11:29 ` [PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode Bin Meng
2021-01-13 17:03 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 12/22] hw/sd: sd.h: Cosmetic change of using spaces Bin Meng
2021-01-13 17:59 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 13/22] hw/sd: Introduce receive_ready() callback Bin Meng
2021-01-13 17:22 ` Alistair Francis
2021-01-14 11:44 ` Philippe Mathieu-Daudé
2020-12-31 11:30 ` [PATCH 14/22] hw/sd: ssi-sd: Support single block write Bin Meng
2021-01-13 18:07 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 15/22] hw/sd: ssi-sd: Support multiple " Bin Meng
2021-01-13 18:11 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 16/22] hw/ssi: Add SiFive SPI controller support Bin Meng
2021-01-13 18:28 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Bin Meng
2021-01-13 18:30 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 18/22] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Bin Meng
2021-01-13 18:32 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 19/22] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Bin Meng
2021-01-13 18:33 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 20/22] docs/system: Sort targets in alphabetical order Bin Meng
2021-01-13 18:33 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 21/22] docs/system: Add RISC-V documentation Bin Meng
2021-01-14 0:11 ` Alistair Francis
2020-12-31 11:30 ` [PATCH 22/22] docs/system: riscv: Add documentation for sifive_u machine Bin Meng
2021-01-14 0:11 ` Alistair Francis
2021-01-02 12:26 ` [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support Pragnesh Patel
2021-01-02 13:15 ` Bin Meng
2021-01-02 13:30 ` Pragnesh Patel
2021-01-02 13:36 ` Bin Meng
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