From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B656FC433F5 for ; Thu, 2 Sep 2021 20:28:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33BD760FDA for ; Thu, 2 Sep 2021 20:28:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 33BD760FDA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:56126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLtJd-00010T-Cx for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 16:28:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtDn-0006Si-Ql for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:22:06 -0400 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]:39784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtDk-00031b-Ap for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:22:03 -0400 Received: by mail-vs1-xe2e.google.com with SMTP id m190so2620264vsm.6 for ; Thu, 02 Sep 2021 13:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=GvLlNSJNAm2e5y1mGaVxHQf2vDe+JRh2+vxn7dLS6Q8=; b=KAI/+L5+S0kJ/VSh7jQq/ZhSQOo/Y911GmvRNUU0fxJLWxJ85cojCKbjQ/burj/sJs 8jP0Mo+OkcAvfbZzxpxBfDoRQC3QMiy/GlaErHVylvIFEh3cpJlZbzjH5m2PRAwwerXV OXAqL887scrUTKwuoqrxNRgf2qIFBo/2ffPsPUduOYRERtdSJym34juUVwc8TR3bRDvY klN5CfYjeiyg7f9cTI+cwpM37PtvTiERyyOqqxVE7mKRrDnVhqo/WeCbBy6mNObuFRnt VKxSJzfthNnRH4iiNWFG4xr7tyicASA2ptsRcd14hkGkZKYOO8DEyDSEYCjGq7TGeECS BVdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=GvLlNSJNAm2e5y1mGaVxHQf2vDe+JRh2+vxn7dLS6Q8=; b=QRfMXXMpVSSLUI6tOzakZdmJJH8VQFeKfL4wCKF2szH3Sup5sO9qwkZ/HZ4DUsoVb3 1kqiGgl9fTdXwe/1dy3lzGsrecTE/fQqywfkzgEW+qteOizk9UW1YmVrUg+6IYdMCiab vX4tWoKeT7LLeIEcdx7goumrHNBF6UubyF5tJG48CKWImcQ+xWICAy6yPgOabVR40XCk sDgycR697Q0LVxPdzZfi3dy4i1jbT/0s16t64mgPXZTmpekQ2Z/9hOXLE7V8KfD68gGu j+yF4tS5TC7XZjsITawcGHg0cqN9FcSDf2A25QzWQGZMur5vN/IyYxTOQ2sNOmuwhHSh vO9w== X-Gm-Message-State: AOAM531EajYDldaoehqFkzh2S6evzeWXfMrR83ndO8Jiz5vLk3hQUMwt O3V+mo5+h5PPh/BbwC3J2ZvR2XBMgEV7RoCCnXjXSA== X-Google-Smtp-Source: ABdhPJz9Xxg/0BFD23MkWO/hkVB0ETcN3oIwNV7EFJeOjoMt7UNEv24P3fYdG5CVmWkysLviz0WQ8pxpCb8jcWjUvqY= X-Received: by 2002:a05:6102:5a:: with SMTP id k26mr4339725vsp.26.1630614119364; Thu, 02 Sep 2021 13:21:59 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-15-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-15-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:21:48 -0600 Message-ID: Subject: Re: [PATCH 14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="00000000000059d41505cb08ef67" Received-SPF: none client-ip=2607:f8b0:4864:20::e2e; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bin Meng , Mark Cave-Ayland , QEMU Developers , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , qemu-ppc , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Kyle Evans , Richard Henderson , Greg Kurz , qemu-arm , Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Chris Wulff , Laurent Vivier , Palmer Dabbelt , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000059d41505cb08ef67 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/mips/tcg/tcg-internal.h | 5 +++-- > target/mips/cpu.c | 2 +- > target/mips/tcg/exception.c | 18 ------------------ > target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++ > target/mips/tcg/user/tlb_helper.c | 5 ----- > 5 files changed, 22 insertions(+), 26 deletions(-) > > Reviewed-by: Warner Losh > diff --git a/target/mips/tcg/tcg-internal.h > b/target/mips/tcg/tcg-internal.h > index 81b14eb219e..c7a77ddccdd 100644 > --- a/target/mips/tcg/tcg-internal.h > +++ b/target/mips/tcg/tcg-internal.h > @@ -18,8 +18,6 @@ > void mips_tcg_init(void); > > void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock > *tb); > -void mips_cpu_do_interrupt(CPUState *cpu); > -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); > bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > @@ -41,6 +39,9 @@ static inline void QEMU_NORETURN > do_raise_exception(CPUMIPSState *env, > > #if !defined(CONFIG_USER_ONLY) > > +void mips_cpu_do_interrupt(CPUState *cpu); > +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); > + > void mmu_init(CPUMIPSState *env, const mips_def_t *def); > > void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t > *pagemask); > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index d426918291a..00e0c55d0e4 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops = =3D { > static const struct TCGCPUOps mips_tcg_ops =3D { > .initialize =3D mips_tcg_init, > .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, > - .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, > .tlb_fill =3D mips_cpu_tlb_fill, > > #if !defined(CONFIG_USER_ONLY) > + .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, > .do_interrupt =3D mips_cpu_do_interrupt, > .do_transaction_failed =3D mips_cpu_do_transaction_failed, > .do_unaligned_access =3D mips_cpu_do_unaligned_access, > diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c > index 4fb8b00711d..7b3026b105b 100644 > --- a/target/mips/tcg/exception.c > +++ b/target/mips/tcg/exception.c > @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const > TranslationBlock *tb) > env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; > } > > -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > -{ > - if (interrupt_request & CPU_INTERRUPT_HARD) { > - MIPSCPU *cpu =3D MIPS_CPU(cs); > - CPUMIPSState *env =3D &cpu->env; > - > - if (cpu_mips_hw_interrupts_enabled(env) && > - cpu_mips_hw_interrupts_pending(env)) { > - /* Raise it */ > - cs->exception_index =3D EXCP_EXT_INTERRUPT; > - env->error_code =3D 0; > - mips_cpu_do_interrupt(cs); > - return true; > - } > - } > - return false; > -} > - > static const char * const excp_names[EXCP_LAST + 1] =3D { > [EXCP_RESET] =3D "reset", > [EXCP_SRESET] =3D "soft reset", > diff --git a/target/mips/tcg/sysemu/tlb_helper.c > b/target/mips/tcg/sysemu/tlb_helper.c > index a150a014ec1..73254d19298 100644 > --- a/target/mips/tcg/sysemu/tlb_helper.c > +++ b/target/mips/tcg/sysemu/tlb_helper.c > @@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs) > cs->exception_index =3D EXCP_NONE; > } > > +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > +{ > + if (interrupt_request & CPU_INTERRUPT_HARD) { > + MIPSCPU *cpu =3D MIPS_CPU(cs); > + CPUMIPSState *env =3D &cpu->env; > + > + if (cpu_mips_hw_interrupts_enabled(env) && > + cpu_mips_hw_interrupts_pending(env)) { > + /* Raise it */ > + cs->exception_index =3D EXCP_EXT_INTERRUPT; > + env->error_code =3D 0; > + mips_cpu_do_interrupt(cs); > + return true; > + } > + } > + return false; > +} > + > void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) > { > CPUState *cs =3D env_cpu(env); > diff --git a/target/mips/tcg/user/tlb_helper.c > b/target/mips/tcg/user/tlb_helper.c > index b835144b820..210c6d529ef 100644 > --- a/target/mips/tcg/user/tlb_helper.c > +++ b/target/mips/tcg/user/tlb_helper.c > @@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int > size, > raise_mmu_exception(env, address, access_type); > do_raise_exception_err(env, cs->exception_index, env->error_code, > retaddr); > } > - > -void mips_cpu_do_interrupt(CPUState *cs) > -{ > - cs->exception_index =3D EXCP_NONE; > -} > -- > 2.31.1 > > --00000000000059d41505cb08ef67 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/mips/tcg/tcg-internal.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 5 +++-- =C2=A0target/mips/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 2 +-
=C2=A0target/mips/tcg/exception.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 18 ---= ---------------
=C2=A0target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++
=C2=A0target/mips/tcg/user/tlb_helper.c=C2=A0 =C2=A0|=C2=A0 5 -----
=C2=A05 files changed, 22 insertions(+), 26 deletions(-)

Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.= h
index 81b14eb219e..c7a77ddccdd 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -18,8 +18,6 @@
=C2=A0void mips_tcg_init(void);

=C2=A0void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBloc= k *tb);
-void mips_cpu_do_interrupt(CPUState *cpu);
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
=C2=A0bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 MMUAccessType access_type, int mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 bool probe, uintptr_t retaddr);
@@ -41,6 +39,9 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMI= PSState *env,

=C2=A0#if !defined(CONFIG_USER_ONLY)

+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
=C2=A0void mmu_init(CPUMIPSState *env, const mips_def_t *def);

=C2=A0void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *p= agemask);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d426918291a..00e0c55d0e4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops =3D = {
=C2=A0static const struct TCGCPUOps mips_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D mips_tcg_init,
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D mips_cpu_synchronize_from_tb,<= br> -=C2=A0 =C2=A0 .cpu_exec_interrupt =3D mips_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D mips_cpu_tlb_fill,

=C2=A0#if !defined(CONFIG_USER_ONLY)
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D mips_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D mips_cpu_do_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_transaction_failed =3D mips_cpu_do_transaction_fail= ed,
=C2=A0 =C2=A0 =C2=A0.do_unaligned_access =3D mips_cpu_do_unaligned_access,<= br> diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
index 4fb8b00711d..7b3026b105b 100644
--- a/target/mips/tcg/exception.c
+++ b/target/mips/tcg/exception.c
@@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tr= anslationBlock *tb)
=C2=A0 =C2=A0 =C2=A0env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK= ;
=C2=A0}

-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
-=C2=A0 =C2=A0 if (interrupt_request & CPU_INTERRUPT_HARD) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 MIPSCPU *cpu =3D MIPS_CPU(cs);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUMIPSState *env =3D &cpu->env;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (cpu_mips_hw_interrupts_enabled(env) &&= amp;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_mips_hw_interrupts_pending(e= nv)) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Raise it */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cs->exception_index =3D EXCP_= EXT_INTERRUPT;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->error_code =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mips_cpu_do_interrupt(cs);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
-=C2=A0 =C2=A0 }
-=C2=A0 =C2=A0 return false;
-}
-
=C2=A0static const char * const excp_names[EXCP_LAST + 1] =3D {
=C2=A0 =C2=A0 =C2=A0[EXCP_RESET] =3D "reset",
=C2=A0 =C2=A0 =C2=A0[EXCP_SRESET] =3D "soft reset",
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c
index a150a014ec1..73254d19298 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0cs->exception_index =3D EXCP_NONE;
=C2=A0}

+bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+=C2=A0 =C2=A0 if (interrupt_request & CPU_INTERRUPT_HARD) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 MIPSCPU *cpu =3D MIPS_CPU(cs);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUMIPSState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (cpu_mips_hw_interrupts_enabled(env) &&= amp;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_mips_hw_interrupts_pending(e= nv)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Raise it */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cs->exception_index =3D EXCP_= EXT_INTERRUPT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->error_code =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mips_cpu_do_interrupt(cs);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return true;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 return false;
+}
+
=C2=A0void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) =C2=A0{
=C2=A0 =C2=A0 =C2=A0CPUState *cs =3D env_cpu(env);
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c
index b835144b820..210c6d529ef 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize,
=C2=A0 =C2=A0 =C2=A0raise_mmu_exception(env, address, access_type);
=C2=A0 =C2=A0 =C2=A0do_raise_exception_err(env, cs->exception_index, env= ->error_code, retaddr);
=C2=A0}
-
-void mips_cpu_do_interrupt(CPUState *cs)
-{
-=C2=A0 =C2=A0 cs->exception_index =3D EXCP_NONE;
-}
--
2.31.1

--00000000000059d41505cb08ef67--