From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AECD8C433F5 for ; Thu, 2 Sep 2021 20:23:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56D386054E for ; Thu, 2 Sep 2021 20:23:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 56D386054E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:41194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLtEo-0007fo-IP for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 16:23:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40576) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtAg-0000eI-Q3 for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:18:50 -0400 Received: from mail-vs1-xe36.google.com ([2607:f8b0:4864:20::e36]:36561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtAc-0000Je-FM for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:18:50 -0400 Received: by mail-vs1-xe36.google.com with SMTP id f6so2611735vsr.3 for ; Thu, 02 Sep 2021 13:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1CW5CoF1GCVAN6grWsJbuTIx9X7F4dCckizxepLv9c0=; b=T8aEmDr/n743PTU9io6Me1pW+KwoMG/w0eurV90C8ngmmayHhJVUNv3kXigIvcmAp2 xJsnW6k9gx2isIUuDkMId2o2EJtUYXJCjwK1HEcL+cBHSrYxUD/FX3Zp/zLs1YHDlfXz P8puRwDCn3oo753wuyiB7WTu0OOvD/Cy9PEcXdYd/LgkFyvmZ6jgngo0sNp5N1y8DIP2 vuHi80S/3V+bCI8+4LGzjRF3b6DFJy98CMCP4jpVOGERt0G6uPeCbwooogDvhsSV4frL 8ShpWoWd+y8yBMo2NJD05+pUxkPbawhdhOxWghq08M/xxpSgLsSg7IX5nTALPFxreGlK wgQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1CW5CoF1GCVAN6grWsJbuTIx9X7F4dCckizxepLv9c0=; b=G/sqtM6hNNc8IhSt05BoxLRnpTF45KotD6cj0d1Kw16KRdfDq1u7PsvYruVtaWUXGD ykeXVRvrmBzRO0XwYMKgB6lgzvtQFqLmrVu51CLtVJ5FVilKH6/DEFlRjeWv3sMPcJs8 FG9PWnJfD9NOZSa3VF3fF0SS4bec6VoOvIqjfvKUuXjG9RywOrZnx2FH5LBVzMrmgIx6 fpz5SIaDzbV5qumO2Np+H0i8OMcb8Z4R8S7LqtBtLp3jc6EDKpUyTCS+Iq2tdRCBDCuC d8Fv/Vj8sRqu1hnUCQk4OnyqGkV1tOIxfmckkpmkGU+UJWQCZXp9J9KqzT4oPHGU7D/b 8ZCQ== X-Gm-Message-State: AOAM531hVWVqp+72ypy8z6Qm+MzjUJnmHAgHAcpuAB9Vt8M46WF5fHwY 5TM9Uk2bhb6hWRITYJQ42fIgANp7ULb3MwkeC3Hmfg== X-Google-Smtp-Source: ABdhPJxfmZYfSKR1QLQkdJgHSEWV4cuWRebtXveUUPYKSjmUgjiGT1esKjb5KEz3tdOaSP2ONbdjMyn6fb8a88EAeDE= X-Received: by 2002:a05:6102:482:: with SMTP id n2mr4008484vsa.53.1630613925491; Thu, 02 Sep 2021 13:18:45 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-12-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-12-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:18:34 -0600 Message-ID: Subject: Re: [PATCH 11/24] target/i386: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000cb87a205cb08e3c6" Received-SPF: none client-ip=2607:f8b0:4864:20::e36; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe36.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bin Meng , Mark Cave-Ayland , QEMU Developers , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , qemu-ppc , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Kyle Evans , Richard Henderson , Greg Kurz , qemu-arm , Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Chris Wulff , Laurent Vivier , Palmer Dabbelt , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000cb87a205cb08e3c6 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/i386/tcg/helper-tcg.h | 2 ++ > target/i386/tcg/seg_helper.c | 10 ++-------- > target/i386/tcg/tcg-cpu.c | 2 +- > 3 files changed, 5 insertions(+), 9 deletions(-) > Reviewed-by: Warner Losh > diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h > index 2510cc244e9..60ca09e95eb 100644 > --- a/target/i386/tcg/helper-tcg.h > +++ b/target/i386/tcg/helper-tcg.h > @@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > > TARGET_PHYS_ADDR_SPACE_BITS); > * @cpu: vCPU the interrupt is to be handled by. > */ > void x86_cpu_do_interrupt(CPUState *cpu); > +#ifndef CONFIG_USER_ONLY > bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); > +#endif > > /* helper.c */ > bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c > index dee7bef68c6..13c6e6ee62e 100644 > --- a/target/i386/tcg/seg_helper.c > +++ b/target/i386/tcg/seg_helper.c > @@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int > intno, int is_hw) > do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); > } > > +#ifndef CONFIG_USER_ONLY > bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > X86CPU *cpu =3D X86_CPU(cs); > @@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > * This is required to make icount-driven execution deterministic. > */ > switch (interrupt_request) { > -#if !defined(CONFIG_USER_ONLY) > case CPU_INTERRUPT_POLL: > cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; > apic_poll_irq(cpu->apic_state); > break; > -#endif > case CPU_INTERRUPT_SIPI: > do_cpu_sipi(cpu); > break; > case CPU_INTERRUPT_SMI: > cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); > cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; > -#ifdef CONFIG_USER_ONLY > - cpu_abort(CPU(cpu), "SMI interrupt: cannot enter SMM in > user-mode"); > -#else > do_smm_enter(cpu); > -#endif /* CONFIG_USER_ONLY */ > break; > case CPU_INTERRUPT_NMI: > cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); > @@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > "Servicing hardware INT=3D0x%02x\n", intno); > do_interrupt_x86_hardirq(env, intno, 1); > break; > -#if !defined(CONFIG_USER_ONLY) > case CPU_INTERRUPT_VIRQ: > /* FIXME: this should respect TPR */ > cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); > @@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > do_interrupt_x86_hardirq(env, intno, 1); > cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; > break; > -#endif > } > > /* Ensure that no TB jump will be modified as the program flow was > changed. */ > return true; > } > +#endif /* CONFIG_USER_ONLY */ > > void helper_lldt(CPUX86State *env, int selector) > { > diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c > index dce800a8953..fd86daf93d2 100644 > --- a/target/i386/tcg/tcg-cpu.c > +++ b/target/i386/tcg/tcg-cpu.c > @@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops =3D { > .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, > .cpu_exec_enter =3D x86_cpu_exec_enter, > .cpu_exec_exit =3D x86_cpu_exec_exit, > - .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, > .tlb_fill =3D x86_cpu_tlb_fill, > #ifdef CONFIG_USER_ONLY > .fake_user_exception =3D x86_cpu_do_interrupt, > #else > .do_interrupt =3D x86_cpu_do_interrupt, > + .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, > .debug_excp_handler =3D breakpoint_handler, > .debug_check_breakpoint =3D x86_debug_check_breakpoint, > #endif /* !CONFIG_USER_ONLY */ > -- > 2.31.1 > > --000000000000cb87a205cb08e3c6 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/i386/tcg/helper-tcg.h |=C2=A0 2 ++
=C2=A0target/i386/tcg/seg_helper.c | 10 ++--------
=C2=A0target/i386/tcg/tcg-cpu.c=C2=A0 =C2=A0 |=C2=A0 2 +-
=C2=A03 files changed, 5 insertions(+), 9 deletions(-)

Reviewed-by: Warner Losh <imp@bsdimp.com>

=C2=A0
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 2510cc244e9..60ca09e95eb 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADD= R_SPACE_BITS);
=C2=A0 * @cpu: vCPU the interrupt is to be handled by.
=C2=A0 */
=C2=A0void x86_cpu_do_interrupt(CPUState *cpu);
+#ifndef CONFIG_USER_ONLY
=C2=A0bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif

=C2=A0/* helper.c */
=C2=A0bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index dee7bef68c6..13c6e6ee62e 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int i= ntno, int is_hw)
=C2=A0 =C2=A0 =C2=A0do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_h= w);
=C2=A0}

+#ifndef CONFIG_USER_ONLY
=C2=A0bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0X86CPU *cpu =3D X86_CPU(cs);
@@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request)
=C2=A0 =C2=A0 =C2=A0 * This is required to make icount-driven execution det= erministic.
=C2=A0 =C2=A0 =C2=A0 */
=C2=A0 =C2=A0 =C2=A0switch (interrupt_request) {
-#if !defined(CONFIG_USER_ONLY)
=C2=A0 =C2=A0 =C2=A0case CPU_INTERRUPT_POLL:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cs->interrupt_request &=3D ~CPU_IN= TERRUPT_POLL;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0apic_poll_irq(cpu->apic_state);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-#endif
=C2=A0 =C2=A0 =C2=A0case CPU_INTERRUPT_SIPI:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_cpu_sipi(cpu);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case CPU_INTERRUPT_SMI:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_svm_check_intercept_param(env, SVM_EX= IT_SMI, 0, 0);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cs->interrupt_request &=3D ~CPU_IN= TERRUPT_SMI;
-#ifdef CONFIG_USER_ONLY
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_abort(CPU(cpu), "SMI interrupt: canno= t enter SMM in user-mode");
-#else
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_smm_enter(cpu);
-#endif /* CONFIG_USER_ONLY */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case CPU_INTERRUPT_NMI:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_svm_check_intercept_param(env, SVM_EX= IT_NMI, 0, 0);
@@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0"Servicing hardware INT=3D0x%02x\n", intno);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_interrupt_x86_hardirq(env, intno, 1);<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-#if !defined(CONFIG_USER_ONLY)
=C2=A0 =C2=A0 =C2=A0case CPU_INTERRUPT_VIRQ:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* FIXME: this should respect TPR */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_svm_check_intercept_param(env, SVM_EX= IT_VINTR, 0, 0);
@@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_interrupt_x86_hardirq(env, intno, 1);<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cs->interrupt_request &=3D ~CPU_IN= TERRUPT_VIRQ;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-#endif
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0/* Ensure that no TB jump will be modified as the progr= am flow was changed.=C2=A0 */
=C2=A0 =C2=A0 =C2=A0return true;
=C2=A0}
+#endif /* CONFIG_USER_ONLY */

=C2=A0void helper_lldt(CPUX86State *env, int selector)
=C2=A0{
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index dce800a8953..fd86daf93d2 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D x86_cpu_synchronize_from_tb, =C2=A0 =C2=A0 =C2=A0.cpu_exec_enter =3D x86_cpu_exec_enter,
=C2=A0 =C2=A0 =C2=A0.cpu_exec_exit =3D x86_cpu_exec_exit,
-=C2=A0 =C2=A0 .cpu_exec_interrupt =3D x86_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D x86_cpu_tlb_fill,
=C2=A0#ifdef CONFIG_USER_ONLY
=C2=A0 =C2=A0 =C2=A0.fake_user_exception =3D x86_cpu_do_interrupt,
=C2=A0#else
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D x86_cpu_do_interrupt,
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D x86_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.debug_excp_handler =3D breakpoint_handler,
=C2=A0 =C2=A0 =C2=A0.debug_check_breakpoint =3D x86_debug_check_breakpoint,=
=C2=A0#endif /* !CONFIG_USER_ONLY */
--
2.31.1

--000000000000cb87a205cb08e3c6--