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boundary="000000000000a86cf2061b7ed620" Received-SPF: none client-ip=2607:f8b0:4864:20::1032; envelope-from=wlosh@bsdimp.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000a86cf2061b7ed620 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Jun 17, 2024 at 10:17=E2=80=AFPM Richard Henderson < richard.henderson@linaro.org> wrote: > On 6/17/24 11:57, Ajeet Singh wrote: > > From: Stacey Son > > > > Addded function to initialize ARM CPU > > and to check if it supports 64 bit mode > > > > Signed-off-by: Ajeet Singh > > Signed-off-by: Stacey Son > > --- > > bsd-user/aarch64/target_arch_cpu.h | 42 +++++++++++++++++++++++++++++= + > > 1 file changed, 42 insertions(+) > > create mode 100644 bsd-user/aarch64/target_arch_cpu.h > > > > diff --git a/bsd-user/aarch64/target_arch_cpu.h > b/bsd-user/aarch64/target_arch_cpu.h > > new file mode 100644 > > index 0000000000..db5c7062b9 > > --- /dev/null > > +++ b/bsd-user/aarch64/target_arch_cpu.h > > @@ -0,0 +1,42 @@ > > +/* > > + * ARM AArch64 cpu init and loop > > + * > > + * Copyright (c) 2015 Stacey Son > > + * > > + * This library is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU Lesser General Public > > + * License as published by the Free Software Foundation; either > > + * version 2 of the License, or (at your option) any later version. > > + * > > + * This library is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + * Lesser General Public License for more details. > > + * > > + * You should have received a copy of the GNU Lesser General Public > > + * License along with this library; if not, see < > http://www.gnu.org/licenses/>. > > + */ > > + > > +#ifndef TARGET_ARCH_CPU_H > > +#define TARGET_ARCH_CPU_H > > + > > +#include "target_arch.h" > > +#include "target/arm/syndrome.h" > > Do you actually need syndrome.h? > It's needed, but not for this chunk. It is needed for patch 2 because we start to use the syndrome functions there to dispatch / decode the traps. So that should be moved to patch 2 in the next round, I think. Also Reviewed-by: Warner Losh since this looks correct and I didn't write it :) Warner > Otherwise, > Reviewed-by: Richard Henderson > > r~ > > > + > > +#define TARGET_DEFAULT_CPU_MODEL "any" > > + > > +static inline void target_cpu_init(CPUARMState *env, > > + struct target_pt_regs *regs) > > +{ > > + int i; > > + > > + if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { > > + fprintf(stderr, "The selected ARM CPU does not support 64 bit > mode\n"); > > + exit(1); > > + } > > + for (i =3D 0; i < 31; i++) { > > + env->xregs[i] =3D regs->regs[i]; > > + } > > + env->pc =3D regs->pc; > > + env->xregs[31] =3D regs->sp; > > +} > > --000000000000a86cf2061b7ed620 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Jun 17, 2024 at 10:17=E2=80= =AFPM Richard Henderson <richard.henderson@linaro.org> wrote:
On 6/17/24 11:57, Ajeet Singh wrote:
> From: Stacey Son <sson@FreeBSD.org>
>
> Addded function to initialize ARM CPU
> and to check if it supports 64 bit mode
>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Signed-off-by: Stacey Son <sson@FreeBSD.org>
> ---
>=C2=A0 =C2=A0bsd-user/aarch64/target_arch_cpu.h | 42 ++++++++++++++++++= ++++++++++++
>=C2=A0 =C2=A01 file changed, 42 insertions(+)
>=C2=A0 =C2=A0create mode 100644 bsd-user/aarch64/target_arch_cpu.h
>
> diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/tar= get_arch_cpu.h
> new file mode 100644
> index 0000000000..db5c7062b9
> --- /dev/null
> +++ b/bsd-user/aarch64/target_arch_cpu.h
> @@ -0,0 +1,42 @@
> +/*
> + *=C2=A0 ARM AArch64 cpu init and loop
> + *
> + * Copyright (c) 2015 Stacey Son
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version. > + *
> + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the= GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see <http://www.gnu= .org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_CPU_H
> +#define TARGET_ARCH_CPU_H
> +
> +#include "target_arch.h"
> +#include "target/arm/syndrome.h"

Do you actually need syndrome.h?

It'= ;s needed, but not for this chunk. It is needed for patch 2 because we star= t to use the syndrome functions there to dispatch / decode the traps.
=
So that should be moved to patch 2 in the next round, I think.

Also

Reviewed-by: Warner Losh &l= t;imp@bsdimp.com>

since this looks correct and I didn't write it :)
Warner
=C2=A0
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> +
> +#define TARGET_DEFAULT_CPU_MODEL "any"
> +
> +static inline void target_cpu_init(CPUARMState *env,
> +=C2=A0 =C2=A0 struct target_pt_regs *regs)
> +{
> +=C2=A0 =C2=A0 int i;
> +
> +=C2=A0 =C2=A0 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 fprintf(stderr, "The selected ARM CP= U does not support 64 bit mode\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 exit(1);
> +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 for (i =3D 0; i < 31; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->xregs[i] =3D regs->regs[i]; > +=C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 env->pc =3D regs->pc;
> +=C2=A0 =C2=A0 env->xregs[31] =3D regs->sp;
> +}

--000000000000a86cf2061b7ed620--