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From: Warner Losh <imp@bsdimp.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Ajeet Singh <itachis6234@gmail.com>,
	qemu-devel@nongnu.org,  Mark Corbin <mark.corbin@embecsom.com>,
	Ajeet Singh <itachis@freebsd.org>,
	 Jessica Clarke <jrtc27@jrtc27.com>,
	Kyle Evans <kevans@freebsd.org>
Subject: Re: [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support
Date: Fri, 2 Aug 2024 18:05:19 -0600	[thread overview]
Message-ID: <CANCZdfpRL7BN1LT-O0Fuw_HiPxujBw6oNqusstnOhGs6NGUh_A@mail.gmail.com> (raw)
In-Reply-To: <4cdcacde-a5f8-4365-bd6c-65e98a77eada@linaro.org>

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On Fri, Aug 2, 2024 at 7:30 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 8/2/24 18:34, Ajeet Singh wrote:
> > From: Mark Corbin <mark.corbin@embecsom.com>
> >
> > Implemented functions for setting up and initializing threads in the
> > RISC-V architecture.
> > The 'target_thread_set_upcall' function sets up the stack pointer,
> > program counter, and function argument for new threads.
> > The 'target_thread_init' function initializes thread registers based on
> > the provided image information.
> >
> > Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> > Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> > Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
> > ---
> >   bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
> >   1 file changed, 47 insertions(+)
> >   create mode 100644 bsd-user/riscv/target_arch_thread.h
> >
> > diff --git a/bsd-user/riscv/target_arch_thread.h
> b/bsd-user/riscv/target_arch_thread.h
> > new file mode 100644
> > index 0000000000..faabb9fb45
> > --- /dev/null
> > +++ b/bsd-user/riscv/target_arch_thread.h
> > @@ -0,0 +1,47 @@
> > +/*
> > + *  RISC-V thread support
> > + *
> > + *  Copyright (c) 2019 Mark Corbin
> > + *
> > + *  This program is free software; you can redistribute it and/or modify
> > + *  it under the terms of the GNU General Public License as published by
> > + *  the Free Software Foundation; either version 2 of the License, or
> > + *  (at your option) any later version.
> > + *
> > + *  This program is distributed in the hope that it will be useful,
> > + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *  GNU General Public License for more details.
> > + *
> > + *  You should have received a copy of the GNU General Public License
> > + *  along with this program; if not, see <http://www.gnu.org/licenses/
> >.
> > + */
> > +
> > +#ifndef TARGET_ARCH_THREAD_H
> > +#define TARGET_ARCH_THREAD_H
> > +
> > +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
> > +static inline void target_thread_set_upcall(CPURISCVState *regs,
> > +    abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
> > +    abi_ulong stack_size)
> > +{
> > +    abi_ulong sp;
> > +
> > +    sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
> > +
> > +    regs->gpr[xSP] = sp;
> > +    regs->pc = entry;
> > +    regs->gpr[xA0] = arg;
> > +}
> > +
> > +/* Compare with exec_setregs() in riscv/riscv/machdep.c */
>
> exec_machdep.c.
>
> > +static inline void target_thread_init(struct target_pt_regs *regs,
> > +    struct image_info *infop)
> > +{
> > +    regs->sepc = infop->entry;
> > +    regs->regs[xRA] = infop->entry;
> > +    regs->regs[10] = infop->start_stack;               /* a0 */
>
> xA0
>
> > +    regs->regs[xSP] = infop->start_stack & ~(16 - 1);
>
> ROUND_DOWN.
>

Oh, I should do a pass through our tree for rounding like this to add this
macro.

Warner


>
> r~
>

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  reply	other threads:[~2024-08-03  0:05 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02  8:34 [PATCH 00/18] bsd-user: Comprehensive RISCV support Ajeet Singh
2024-08-02  8:34 ` [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-02 12:41   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-02 12:54   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-02 12:58   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-02 13:01   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 05/18] bsd-user: Add prototype for " Ajeet Singh
2024-08-02 13:04   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-02 13:13   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-02 13:20   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-02 13:24   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 09/18] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-02 13:27   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 10/18] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-02 13:30   ` Richard Henderson
2024-08-03  0:05     ` Warner Losh [this message]
2024-08-02  8:34 ` [PATCH 11/18] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-02 13:33   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 12/18] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-02 13:35   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 13/18] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-02 13:35   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 14/18] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-02 13:38   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 15/18] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-02 13:46   ` Richard Henderson
2024-08-03  0:04     ` Warner Losh
2024-08-03  9:33       ` Richard Henderson
2024-08-02  8:34 ` [PATCH 16/18] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-02 13:47   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 17/18] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-02 13:48   ` Richard Henderson
2024-08-02  8:34 ` [PATCH 18/18] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-08-02 13:50   ` Richard Henderson

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