From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3F96C433EF for ; Fri, 15 Oct 2021 18:48:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1559361041 for ; Fri, 15 Oct 2021 18:48:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1559361041 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:43170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mbSFz-00023d-3P for qemu-devel@archiver.kernel.org; Fri, 15 Oct 2021 14:48:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mbSCs-0000Og-OG for qemu-devel@nongnu.org; Fri, 15 Oct 2021 14:45:26 -0400 Received: from mail-vk1-xa36.google.com ([2607:f8b0:4864:20::a36]:42551) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mbSCq-0006cp-Pg for qemu-devel@nongnu.org; Fri, 15 Oct 2021 14:45:26 -0400 Received: by mail-vk1-xa36.google.com with SMTP id o42so5597810vkf.9 for ; Fri, 15 Oct 2021 11:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8FzoarPMYGUcIi9Dd1njX18tUzdQ9keLkFtvRWbsDUw=; b=Z4dzvQxOVotfU4r0ZbsHk1nVyc50M9jFJx01WXT3kwI0ITueEJjskia2ewVFGYeo41 4KUpRpkRegIdSomDA4z4pk9ZT6or80Pfy6ElwWIJ6K93ReO1KQQqn39dgbNIcZ+Suzi0 bFP95Ml/ujsuUVq/RLKrbq4CdZty6NFQXK/I2GgbvOiveu/xRfyrnsq91dxgj7G4YoA/ v8IsRtLtlRbP7ymYOhTIUsfS6T0gUqfhJjgoxY2/Mnaw21Rud6z9uJnutCm/dqTnCRJ4 Ox0WQSlkDf/K/un87wjuwHxuf2YHzdD6vfQ8hNY5XmhwVf4J3/aCULPL4n2Qc4q20aCX mNbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8FzoarPMYGUcIi9Dd1njX18tUzdQ9keLkFtvRWbsDUw=; b=rm7iShrglM7g0pwjvS9Xx3lbuQxTOuC6nZTHIpZSZxQp7r+/McLmPfucISdQIZ3be2 fzjQGtRHjXng3yUjoidDe6Px9oDcIqmSGHuH7602JRX5N2G78IhRksb+dp2QKb0UWoJU O9CzRPHqjIuBQlQg/m36qzX1G80pd6PAPVRq1tuvSWvEF8XZLxls9PnE+9+IGy9WjXri pzNBItKxeDllURFCvVjUsLOdkeQMOCLNBY8K/ONOXLAisxz/Knm+Uo+wfdu0psxlrIQE O7XfsnWxIrBdoD39B1vCxic6gnHJU7tFlVb1/eRo+wuhxf365rc50J505KYRtptQ4R6b heNQ== X-Gm-Message-State: AOAM530v4YVg0l07JyKi5laycEoTtR31scYQQmkIHahfsM4NsJZlZ7LR +EhnjZqAapL1kBnBQO0buvkKRwKDxSfcxRPvFRLtyw== X-Google-Smtp-Source: ABdhPJyaxmN54utXUg9yxVtJut0gu1YzcHElme6Zo4D9Aj/xU6DlnOhLghTEuo7ctvv+3H78QpXgt7DFwbcY8ngSlKw= X-Received: by 2002:a05:6122:180d:: with SMTP id ay13mr3861165vkb.21.1634323523665; Fri, 15 Oct 2021 11:45:23 -0700 (PDT) MIME-Version: 1.0 References: <20211015041053.2769193-1-richard.henderson@linaro.org> <20211015041053.2769193-35-richard.henderson@linaro.org> In-Reply-To: <20211015041053.2769193-35-richard.henderson@linaro.org> From: Warner Losh Date: Fri, 15 Oct 2021 12:45:12 -0600 Message-ID: Subject: Re: [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv To: Richard Henderson Content-Type: multipart/alternative; boundary="00000000000013938705ce6899bb" Received-SPF: none client-ip=2607:f8b0:4864:20::a36; envelope-from=wlosh@bsdimp.com; helo=mail-vk1-xa36.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000013938705ce6899bb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson < richard.henderson@linaro.org> wrote: > Record DAR, DSISR, and exception_index. That last means > that we must exit to cpu_loop ourselves, instead of letting > exception_index being overwritten. > > This is exactly what the user-mode ppc_cpu_tlb_fill does, > so simply rename it as ppc_cpu_record_sigsegv. > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Richard Henderson > --- > target/ppc/cpu.h | 3 --- > target/ppc/internal.h | 9 +++++++++ > target/ppc/cpu_init.c | 6 ++++-- > target/ppc/user_only_helper.c | 15 +++++++++++---- > 4 files changed, 24 insertions(+), 9 deletions(-) > Reviewed-by: Warner Losh > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index baa4e7c34d..2242d57718 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu; > > > /***********************************************************************= ******/ > void ppc_translate_init(void); > -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > - MMUAccessType access_type, int mmu_idx, > - bool probe, uintptr_t retaddr); > > #if !defined(CONFIG_USER_ONLY) > void ppc_store_sdr1(CPUPPCState *env, target_ulong value); > diff --git a/target/ppc/internal.h b/target/ppc/internal.h > index 55284369f5..339974b7d8 100644 > --- a/target/ppc/internal.h > +++ b/target/ppc/internal.h > @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0= ) > #define PTE_PTEM_MASK 0x7FFFFFBF > #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) > > +#ifdef CONFIG_USER_ONLY > +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, > + MMUAccessType access_type, > + bool maperr, uintptr_t ra); > +#else > +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > + MMUAccessType access_type, int mmu_idx, > + bool probe, uintptr_t retaddr); > +#endif > > #endif /* PPC_INTERNAL_H */ > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 6aad01d1d3..ec8da08f0b 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = =3D { > > static const struct TCGCPUOps ppc_tcg_ops =3D { > .initialize =3D ppc_translate_init, > - .tlb_fill =3D ppc_cpu_tlb_fill, > > -#ifndef CONFIG_USER_ONLY > +#ifdef CONFIG_USER_ONLY > + .record_sigsegv =3D ppc_cpu_record_sigsegv, > +#else > + .tlb_fill =3D ppc_cpu_tlb_fill, > .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, > .do_interrupt =3D ppc_cpu_do_interrupt, > .cpu_exec_enter =3D ppc_cpu_exec_enter, > diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.= c > index aa3f867596..7ff76f7a06 100644 > --- a/target/ppc/user_only_helper.c > +++ b/target/ppc/user_only_helper.c > @@ -21,16 +21,23 @@ > #include "qemu/osdep.h" > #include "cpu.h" > #include "exec/exec-all.h" > +#include "internal.h" > > - > -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > - MMUAccessType access_type, int mmu_idx, > - bool probe, uintptr_t retaddr) > +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, > + MMUAccessType access_type, > + bool maperr, uintptr_t retaddr) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > CPUPPCState *env =3D &cpu->env; > int exception, error_code; > > + /* > + * Both DSISR and the "trap number" (exception vector offset, > + * looked up from exception_index) are present in the linux-user > + * signal frame. > + * FIXME: we don't actually populate the trap number properly. > + * It would be easiest to fill in an env->trap value now. > + */ > I think the same concerns apply to bsd-user, though the details differ since trap frames only fill in information relevant to the specific trap type. This may require some refinement in the future when it's time to upstream bsd-user ppc support. I'll revisit this, though, when that time comes. Warner > if (access_type =3D=3D MMU_INST_FETCH) { > exception =3D POWERPC_EXCP_ISI; > error_code =3D 0x40000000; > -- > 2.25.1 > > --00000000000013938705ce6899bb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Oct 14, 2021 at 10:11 PM Rich= ard Henderson <richard.h= enderson@linaro.org> wrote:
Record DAR, DSISR, and exception_index.=C2=A0 That last = means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.

This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.

Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
=C2=A0target/ppc/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 3 ---
=C2=A0target/ppc/internal.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 9 ++++= +++++
=C2=A0target/ppc/cpu_init.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 6 ++++= --
=C2=A0target/ppc/user_only_helper.c | 15 +++++++++++----
=C2=A04 files changed, 24 insertions(+), 9 deletions(-)

Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index baa4e7c34d..2242d57718 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu;

=C2=A0/********************************************************************= *********/
=C2=A0void ppc_translate_init(void);
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 MMUAccessType access_type, int mmu_idx,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 bool probe, uintptr_t retaddr);

=C2=A0#if !defined(CONFIG_USER_ONLY)
=C2=A0void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 55284369f5..339974b7d8 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)<= br> =C2=A0#define PTE_PTEM_MASK 0x7FFFFFBF
=C2=A0#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)

+#ifdef CONFIG_USER_ONLY
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 MMUAccessType access_type,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 bool maperr, uintptr_t ra);
+#else
+bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 MMUAccessType access_type, int mmu_idx,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 bool probe, uintptr_t retaddr);
+#endif

=C2=A0#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6aad01d1d3..ec8da08f0b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D = {

=C2=A0static const struct TCGCPUOps ppc_tcg_ops =3D {
=C2=A0 =C2=A0.initialize =3D ppc_translate_init,
-=C2=A0 .tlb_fill =3D ppc_cpu_tlb_fill,

-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+=C2=A0 .record_sigsegv =3D ppc_cpu_record_sigsegv,
+#else
+=C2=A0 .tlb_fill =3D ppc_cpu_tlb_fill,
=C2=A0 =C2=A0.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt,
=C2=A0 =C2=A0.do_interrupt =3D ppc_cpu_do_interrupt,
=C2=A0 =C2=A0.cpu_exec_enter =3D ppc_cpu_exec_enter,
diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c<= br> index aa3f867596..7ff76f7a06 100644
--- a/target/ppc/user_only_helper.c
+++ b/target/ppc/user_only_helper.c
@@ -21,16 +21,23 @@
=C2=A0#include "qemu/osdep.h"
=C2=A0#include "cpu.h"
=C2=A0#include "exec/exec-all.h"
+#include "internal.h"

-
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 MMUAccessType access_type, int mmu_idx,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 bool probe, uintptr_t retaddr)
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 MMUAccessType access_type,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 bool maperr, uintptr_t retaddr)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0PowerPCCPU *cpu =3D POWERPC_CPU(cs);
=C2=A0 =C2=A0 =C2=A0CPUPPCState *env =3D &cpu->env;
=C2=A0 =C2=A0 =C2=A0int exception, error_code;

+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* Both DSISR and the "trap number" (exceptio= n vector offset,
+=C2=A0 =C2=A0 =C2=A0* looked up from exception_index) are present in the l= inux-user
+=C2=A0 =C2=A0 =C2=A0* signal frame.
+=C2=A0 =C2=A0 =C2=A0* FIXME: we don't actually populate the trap numbe= r properly.
+=C2=A0 =C2=A0 =C2=A0* It would be easiest to fill in an env->trap value= now.
+=C2=A0 =C2=A0 =C2=A0*/

I think the sam= e concerns apply to bsd-user, though
the details differ since tra= p frames only fill in information
relevant to the specific trap t= ype. This may require some
refinement in the future when it's= time to upstream bsd-user
ppc support. I'll revisit this, th= ough, when that time comes.

Warner
=C2= =A0
=C2=A0 =C2=A0 =C2=A0if (access_type =3D=3D MMU_INST_FETCH) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0exception =3D POWERPC_EXCP_ISI;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0error_code =3D 0x40000000;
--
2.25.1

--00000000000013938705ce6899bb--