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Thu, 27 Jan 2022 07:40:25 -0800 (PST) MIME-Version: 1.0 References: <20220125012947.14974-1-imp@bsdimp.com> <20220125012947.14974-15-imp@bsdimp.com> <8d876840-8743-0e8b-c477-ca8a6e067d8c@linaro.org> In-Reply-To: <8d876840-8743-0e8b-c477-ca8a6e067d8c@linaro.org> From: Warner Losh Date: Thu, 27 Jan 2022 08:40:14 -0700 Message-ID: Subject: Re: [PATCH v2 14/40] bsd-user/arm/target_arch_cpu.h: Use force_sig_fault for EXCP_UDEF To: Richard Henderson Content-Type: multipart/alternative; boundary="0000000000000e1b4605d69223fa" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::929 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::929; envelope-from=wlosh@bsdimp.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Konrad Witaszczyk , QEMU Developers , Kyle Evans , Jessica Clarke Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000000e1b4605d69223fa Content-Type: text/plain; charset="UTF-8" On Wed, Jan 26, 2022 at 11:27 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 1/25/22 12:29, Warner Losh wrote: > > + case EXCP_NOCP: > > + case EXCP_INVSTATE: > > + /* > > + * See arm/arm/undefined.c undefinedinstruction(); > > + * > > + * A number of details aren't emulated (they likely don't > matter): > > + * o Misaligned PC generates ILL_ILLADR > > As I mentioned, misaligned pc will not come here for qemu. > In the Arm ARM, see aarch32/functions/registers/BXWritePC: > > // For branches to an unaligned PC counter in A32 state, the processor > takes the branch > // and does one of: > // * Forces the address to be aligned > // * Leaves the PC unaligned, meaning the target generates a PC Alignment > fault. > > The hardware will either refuse to allow bit 1 to be set when bit 0 is > clear, OR it will > generate a PREFETCH_DATA_ABORT for Alignment. > > QEMU will do the latter. > Ah, right. I'd meant to update the comments and it slipped my mind. I'll note that this can't happen in qemu. > > Otherwise, > Reviewed-by: Richard Henderson > Thanks for this (and all the other) review and feedback. Warner > r~ > --0000000000000e1b4605d69223fa Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Jan 26, 2022 at 11:27 PM Rich= ard Henderson <richard.h= enderson@linaro.org> wrote:
On 1/25/22 12:29, Warner Losh wrote:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case EXCP_NOCP:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 case EXCP_INVSTATE:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* See arm/arm/undefin= ed.c undefinedinstruction();
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* A number of details= aren't emulated (they likely don't matter):
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* o Misaligned PC gen= erates ILL_ILLADR

As I mentioned, misaligned pc will not come here for qemu.
In the Arm ARM, see aarch32/functions/registers/BXWritePC:

// For branches to an unaligned PC counter in A32 state, the processor take= s the branch
// and does one of:
// * Forces the address to be aligned
// * Leaves the PC unaligned, meaning the target generates a PC Alignment f= ault.

The hardware will either refuse to allow bit 1 to be set when bit 0 is clea= r, OR it will
generate a PREFETCH_DATA_ABORT for Alignment.

QEMU will do the latter.

Ah, right. I&#= 39;d meant to update the comments and it slipped my mind. I'll note
that this can't happen in qemu.
=C2=A0

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks for this (and all the other) review and feed= back.

Warner


=C2=A0
r~
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