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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=etDdz7r9ka1d6Iyc8TT+35IHert1sULZbtZ+2T+ACms=; b=B+JsLp26sBtsN7oxjkqald/2QDrpL10NKpzUBG/LL3cgdRmaPIBXXWjhtFWoSfwvyk SQus/JrYhfuYPqwnKdXJsAo2IxwE8Ur43V/Wh0RgQVaUWL1VDnPdr/fepG2npjVD+gD2 of+g6/xJGLuOmyXGWOg04hGJ0cab1OmUG2CD7BDCIiYlKR1ic2A/XLmcLfABzBuMAInR r/pOvq/KjLfp5ejpfUX1EPG0JMET2nkhb55bs0WZk3eZXyuMWqotmRTqg2Xy18p3imH6 Xow0BoEPaqG/k+iLi00jzMSbAhi9bgeeHEgUAme/n/OOIcaEyMnMqArkD8WdEW4sMJh3 IZ5w== X-Gm-Message-State: AOAM533CqBCZf09pIAiwbT0S5CuKkt5HnolYoF9ZP2Gis6VgO9SjJsf2 7+JvGVwEjfELonapG5Hi6g07/VHWyDs0Iwgt3ZGNpw== X-Google-Smtp-Source: ABdhPJzMczPV71y1l7fTwU5vOVPZD/4ooeSrYm/TY7+oxHsJlZjvKHPDDFiJ5PdWfPe4w/pmHKkC2uc08nEcP400d4U= X-Received: by 2002:a9f:21d7:: with SMTP id 81mr37066813uac.39.1636070395005; Thu, 04 Nov 2021 16:59:55 -0700 (PDT) MIME-Version: 1.0 References: <20211104140536.42573-1-imp@bsdimp.com> <20211104140536.42573-24-imp@bsdimp.com> In-Reply-To: From: Warner Losh Date: Thu, 4 Nov 2021 17:59:43 -0600 Message-ID: Subject: Re: [PATCH v3 23/29] bsd-user/arm/target_arch_signal.h: arm set_mcontext To: Richard Henderson Content-Type: multipart/alternative; boundary="000000000000b8e4d505cfff52ce" Received-SPF: none client-ip=2607:f8b0:4864:20::935; envelope-from=wlosh@bsdimp.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stacey Son , QEMU Trivial , Kyle Evans , Michael Tokarev , Philippe Mathieu-Daude , QEMU Developers , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000b8e4d505cfff52ce Content-Type: text/plain; charset="UTF-8" On Thu, Nov 4, 2021 at 12:43 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 11/4/21 10:05 AM, Warner Losh wrote: > > + /* > > + * Make sure T mode matches the PC's notion of thumb mode, although > > + * FreeBSD lets the processor sort this out, so we may need remove > > + * this check, or generate a signal... > > + */ > > + if (!!(tswap32(gr[TARGET_REG_PC]) & 1) != !!(cpsr & CPSR_T)) { > > + return -TARGET_EINVAL; > > + } > > I've had a read through the Arm ARM for "movs pc, lr", which is how > swi_exit returns to > userspace: > > CPSRWriteByInstr(SPSR[], '1111', TRUE); > ... > BranchWritePC(result); > > So the CPSR gets written first, which sets the T bit, and thus the result > of > CurrentInstrSet(), then > > BranchWritePC(bits(32) address) > if CurrentInstrSet() == InstrSet_ARM then > if ArchVersion() < 6 && address<1:0> != '00' then UNPREDICTABLE; > BranchTo(address<31:2>:'00'); > ... > else > BranchTo(address<31:1>:'0'); > > > + env->regs[15] = tswap32(gr[TARGET_REG_PC]); > > So this should mask the low 1 or 2 bits depending on cpsr & CPSR_T. > Will do. Thanks for all the patient explanations. Warner > r~ > --000000000000b8e4d505cfff52ce Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Nov 4, 2021 at 12:43 PM Richa= rd Henderson <richard.he= nderson@linaro.org> wrote:
On 11/4/21 10:05 AM, Warner Losh wrote:
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Make sure T mode matches the PC's notion of= thumb mode, although
> +=C2=A0 =C2=A0 =C2=A0* FreeBSD lets the processor sort this out, so we= may need remove
> +=C2=A0 =C2=A0 =C2=A0* this check, or generate a signal...
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if (!!(tswap32(gr[TARGET_REG_PC]) & 1) !=3D !!(cpsr= & CPSR_T)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return -TARGET_EINVAL;
> +=C2=A0 =C2=A0 }

I've had a read through the Arm ARM for "movs pc, lr", which = is how swi_exit returns to
userspace:

=C2=A0 =C2=A0 =C2=A0CPSRWriteByInstr(SPSR[], '1111', TRUE);
=C2=A0 =C2=A0 =C2=A0...
=C2=A0 =C2=A0 =C2=A0BranchWritePC(result);

So the CPSR gets written first, which sets the T bit, and thus the result o= f
CurrentInstrSet(), then

BranchWritePC(bits(32) address)
=C2=A0 =C2=A0if CurrentInstrSet() =3D=3D InstrSet_ARM then
=C2=A0 =C2=A0 =C2=A0if ArchVersion() < 6 && address<1:0> != =3D '00' then UNPREDICTABLE;
=C2=A0 =C2=A0 =C2=A0BranchTo(address<31:2>:'00');
=C2=A0 =C2=A0...
=C2=A0 =C2=A0else
=C2=A0 =C2=A0 =C2=A0BranchTo(address<31:1>:'0');

> +=C2=A0 =C2=A0 env->regs[15] =3D tswap32(gr[TARGET_REG_PC]);

So this should mask the low 1 or 2 bits depending on cpsr & CPSR_T.
=

Will do. Thanks for all the patient explan= ations.

Warner
=C2=A0
r~
--000000000000b8e4d505cfff52ce--