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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jul 21, 2020 at 10:41 AM Bin Meng wrote: > > Hi Zong, > > On Mon, Jul 20, 2020 at 5:46 PM Zong Li wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > implementation, the second parameter of pmp_write_cfg is > > "reg_index * sizeof(target_ulong)", and we get the the result > > which is started from 16 if reg_index is 2, but we expect that > > it should be started from 8. Separate the implementation for > > RV32 and RV64 respectively. > > > > Signed-off-by: Zong Li > > --- > > target/riscv/pmp.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > > index 2a2b9f5363..adcdd411e6 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -320,8 +320,13 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, > > > > for (i = 0; i < sizeof(target_ulong); i++) { > > cfg_val = (val >> 8 * i) & 0xff; > > +#if defined(TARGET_RISCV32) > > pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, > > cfg_val); > > +#elif defined(TARGET_RISCV64) > > + pmp_write_cfg(env, ((reg_index >> 1) * sizeof(target_ulong)) + i, > > + cfg_val); > > +#endif > > Can you please simplify this by shifting reg_index outside the for > loop for RV64? > OK, that would be great. Change it in the next version, thanks. > > } > > } > > > > @@ -336,7 +341,11 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) > > target_ulong val = 0; > > > > for (i = 0; i < sizeof(target_ulong); i++) { > > +#if defined(TARGET_RISCV32) > > val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); > > +#elif defined(TARGET_RISCV64) > > + val = pmp_read_cfg(env, ((reg_index >> 1) * sizeof(target_ulong)) + i); > > +#endif > > cfg_val |= (val << (i * 8)); > > } > > trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); > > Regards, > Bin