From: Max Chou <max.chou@sifive.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions
Date: Mon, 7 Jul 2025 18:37:46 +0800 [thread overview]
Message-ID: <CANiaA1uoJu0vFQVrFrww4t5Sysa1XqM1esra0YEbStRxkGEoTA@mail.gmail.com> (raw)
In-Reply-To: <fdffc8af-897c-4f2d-a046-2b6c2bc370c4@ventanamicro.com>
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Hi Daniel,
Thanks for the question.
Yes, you are right.
And I find that I miss some patches for the part that you mentioned here.
I'll update this patchset for it.
Thanks,
Max
On Wed, Jul 2, 2025 at 10:48 PM Daniel Henrique Barboza <
dbarboza@ventanamicro.com> wrote:
>
>
> On 6/27/25 10:21 AM, Max Chou wrote:
> > According to the RISC-V instruction set manual, the minimum VLEN needs
> > to respect the following extensions:
> >
> > Extension Minimum VLEN
> > * V 128
> > * Zve64[d|f|x] 64
> > * Zve32[f|x] 32
> >
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> > target/riscv/tcg/tcg-cpu.c | 13 +++++++++++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index 163e7ce3642..187534009dd 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -416,12 +416,21 @@ static void
> riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> > static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig
> *cfg,
> > Error **errp)
> > {
> > + uint32_t min_vlen;
> > uint32_t vlen = cfg->vlenb << 3;
> >
> > - if (vlen > RV_VLEN_MAX || vlen < 128) {
> > + if (riscv_has_ext(env, RVV)) {
> > + min_vlen = 128;
> > + } else if (cfg->ext_zve64x) {
> > + min_vlen = 64;
> > + } else if (cfg->ext_zve32x) {
> > + min_vlen = 32;
> > + }
>
> At this moment this is how we're calling riscv_cpu_validate_v():
>
> if (riscv_has_ext(env, RVV)) {
> riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> return;
> }
> }
>
>
> riscv_has_ext(env, RVV) is always true inside the function. The code above
> will
> always result in min_vlen = 128 because of the 'else if' chaining.
>
> IIUC the idea of the patch, what you want is something like:
>
> > + uint32_t min_vlen = 128;
> > uint32_t vlen = cfg->vlenb << 3;
> >
> > - if (vlen > RV_VLEN_MAX || vlen < 128) {
> > + if (cfg->ext_zve64x) {
> > + min_vlen = 64;
> > + } else if (cfg->ext_zve32x) {
> > + min_vlen = 32;
> > + }
>
> I.e. init min_vlen to 128 (since RVV is always true) and then change it
> according to
> zve64x and zve32x.
>
>
> Thanks,
>
> Daniel
>
>
>
> > +
> > + if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
> > error_setg(errp,
> > "Vector extension implementation only supports VLEN
> "
> > - "in the range [128, %d]", RV_VLEN_MAX);
> > + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
> > return;
> > }
> >
>
>
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prev parent reply other threads:[~2025-07-07 10:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-27 13:21 [PATCH] target/riscv: rvv: Minimum VLEN needs to respect V/Zve extensions Max Chou
2025-07-01 4:11 ` Nutty Liu
2025-07-02 14:48 ` Daniel Henrique Barboza
2025-07-07 10:37 ` Max Chou [this message]
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