From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 532FAC77B7A for ; Wed, 24 May 2023 05:36:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1hAF-0004kW-Aq; Wed, 24 May 2023 01:36:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1h9w-0004jb-7U for qemu-devel@nongnu.org; Wed, 24 May 2023 01:35:40 -0400 Received: from mail-vs1-xe32.google.com ([2607:f8b0:4864:20::e32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1h9t-0005Vg-LX for qemu-devel@nongnu.org; Wed, 24 May 2023 01:35:39 -0400 Received: by mail-vs1-xe32.google.com with SMTP id ada2fe7eead31-43943447fb9so169846137.2 for ; Tue, 23 May 2023 22:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1684906536; x=1687498536; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HcmmS6W1Dr1XG/1SXPF0Jm9xXiHLTJHeCt9Suq6wYZU=; b=OtCN0qOnTJ3TJQFu57ucLnPLVHoWNq4c4kEefLdjBpXRyiiQ+m7pYRKi40VmJYlRpt XU/5Q2Juh5ksUJj/SqDfKO1StBx8SqIvwqJOUyjLf9SxQzCKUTDPV6TpFuZHZPaxQ/xt R3kjtdCUMAmJ+zXYgx/swf260hdpD/GlYcgeUgztEohxm2oZLZikE1skXhs/Q2m02gUX QWx5KxfTQEi72+ho9IJ82Pzsy1CsQW9Pb12GhpsOwEZf1mbQtXb6lK7g6HYZic0T+mgY sLvUi8TZl04el82itRHj6Eq3D+aGLvht27DHJwllnRkbZvGjfGqozksfZWqQoLPuvqYd twmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684906536; x=1687498536; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HcmmS6W1Dr1XG/1SXPF0Jm9xXiHLTJHeCt9Suq6wYZU=; b=UAhFpz8sUSM4ckWu9eD/ClMw0CRfONpOTG34cmhZNRF9D1KIvciPuik9EI1o+NXH2I cR0JJVfsIbqNDUc2vcjSDGWt0DK3RAC+pvANqPiR6wQ/ZQHs4INDGiRa+pznXq8jZ13b HlL03BqASwR+7JzixYDDREC6HJ2jgVCh9NlcKJrtNY2CMcGsS2E2iePNg/Pr3Zcl/NDV Q09TXfzmwwr457hEt4fCU/i4muuScdgOjTsucNYxxRCQWVty214Hm5NgXd/aHjpxGhpZ ToCK+oOoPNjP6rx4gltm6DkaX4KWDYXuaug+G8+setZT5tTPgb3UlQk1jNadWvRiyAC6 L7cA== X-Gm-Message-State: AC+VfDyQq60ATesLlE0exyB0eJbZVmajp1jDVPYsmlT5EapgwZSEG+a4 K3P2h91f6dv/FezHBS8bms7WJtibDOGtySwVqgeYjg== X-Google-Smtp-Source: ACHHUZ4RcZBa9l9/0yjZVcY2XARhUp1iJKozEz3rj9RShhzcBREEajc2XckGBMdGeAkZawrucSkwY3b+rfiUDsr5NMU= X-Received: by 2002:a05:6102:3177:b0:42c:9864:3adf with SMTP id l23-20020a056102317700b0042c98643adfmr4081048vsm.31.1684906536373; Tue, 23 May 2023 22:35:36 -0700 (PDT) MIME-Version: 1.0 References: <20230523114454.717708-1-tommy.wu@sifive.com> <20230523114454.717708-2-tommy.wu@sifive.com> <5d3558a0-8b7f-8b84-a4e0-a6f4404a56b6@iscas.ac.cn> In-Reply-To: From: Tommy Wu Date: Wed, 24 May 2023 13:35:26 +0800 Message-ID: Subject: Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml. To: Weiwei Li Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, frank.chang@sifive.com, alistair.francis@wdc.com, apatel@ventanamicro.com, palmer@rivosinc.com, dbarboza@ventanamicro.com, bin.meng@windriver.com, zhiwei_liu@linux.alibaba.com Content-Type: multipart/alternative; boundary="00000000000094af6605fc69df33" Received-SPF: pass client-ip=2607:f8b0:4864:20::e32; envelope-from=tommy.wu@sifive.com; helo=mail-vs1-xe32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_KAM_HTML_FONT_INVALID=0.01, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000094af6605fc69df33 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi WeiWei Li, When the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml` for the first time with the correct `base_reg` value. code flow : riscv_cpu_realize =E2=86=92 riscv_cpu_register_gdb_regs_for_features =E2=86=92 riscv_gen_dynamic_csr_xml The functionality of `cpu->dyn_csr_base_reg` is to record the `base_reg` from `riscv_cpu_register_gdb_regs_for_features`. When we try to refresh the dynamic CSRs xml, we will call the function `riscv_gen_dynamic_csr_xml` for the second time, and then we can give the correct `base_reg` value to the function `riscv_gen_dynamic_csr_xml`, because we've record this value in the ` cpu->dyn_csr_base_reg`. Best Regards, Tommy On Wed, May 24, 2023 at 10:10=E2=80=AFAM Weiwei Li w= rote: > > On 2023/5/24 09:59, Tommy Wu wrote: > > Hi Weiwei Li, > > > > `dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml` > > We can initialize this variable when the cpu is realized. > I didn't find this initialization in following code. > > And used this variable in `riscv_refresh_dynamic_csr_xml`. > > That's my question. In riscv_refresh_dynamic_csr_xml() , > cpu->dyn_csr_base_reg is passed to riscv_gen_dynamic_csr_xml() as base_re= g. > > And then base_reg is assigned to cpu->dyn_csr_base_reg again in it. So > it's unchanged in this progress. > > Another question is dyn_csr_base_reg seems have no additional function > currently. > > Regards, > > Weiwei Li > > > > > Best regards, > > Tommy > > > > > > On Tue, May 23, 2023 at 10:38=E2=80=AFPM Weiwei Li wrote: > > > > > > On 2023/5/23 19:44, Tommy Wu wrote: > > > When we change the cpu extension state after the cpu is > > > realized, we cannot print the value of some CSRs in the remote > > > gdb debugger. The root cause is that the dynamic CSR xml is > > > generated when the cpu is realized. > > > > > > This patch add a function to refresh the dynamic CSR xml after > > > the cpu is realized. > > > > > > Signed-off-by: Tommy Wu > > > Reviewed-by: Frank Chang > > > --- > > > target/riscv/cpu.h | 2 ++ > > > target/riscv/gdbstub.c | 12 ++++++++++++ > > > 2 files changed, 14 insertions(+) > > > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > > index de7e43126a..dc8e592275 100644 > > > --- a/target/riscv/cpu.h > > > +++ b/target/riscv/cpu.h > > > @@ -494,6 +494,7 @@ struct ArchCPU { > > > CPUNegativeOffsetState neg; > > > CPURISCVState env; > > > > > > + int dyn_csr_base_reg; > > > > dyn_csr_base_reg seems have no additional effect on the function. > > > > And It remains unmodified in following > > riscv_refresh_dynamic_csr_xml(). > > > > Regards, > > > > Weiwei Li > > > > > char *dyn_csr_xml; > > > char *dyn_vreg_xml; > > > > > > @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno, > > riscv_csr_operations *ops); > > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > +void riscv_refresh_dynamic_csr_xml(CPUState *cs); > > > > > > uint8_t satp_mode_max_from_map(uint32_t map); > > > const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > > > index 524bede865..9e97ee2c35 100644 > > > --- a/target/riscv/gdbstub.c > > > +++ b/target/riscv/gdbstub.c > > > @@ -230,6 +230,8 @@ static int > > riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) > > > bitsize =3D 64; > > > } > > > > > > + cpu->dyn_csr_base_reg =3D base_reg; > > > + > > > g_string_printf(s, ""); > > > g_string_append_printf(s, " > \"gdb-target.dtd\">"); > > > g_string_append_printf(s, " > name=3D\"org.gnu.gdb.riscv.csr\">"); > > > @@ -349,3 +351,13 @@ void > > riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > > > "riscv-csr.xml", 0); > > > } > > > } > > > + > > > +void riscv_refresh_dynamic_csr_xml(CPUState *cs) > > > +{ > > > + RISCVCPU *cpu =3D RISCV_CPU(cs); > > > + if (!cpu->dyn_csr_xml) { > > > + g_assert_not_reached(); > > > + } > > > + g_free(cpu->dyn_csr_xml); > > > + riscv_gen_dynamic_csr_xml(cs, cpu->dyn_csr_base_reg); > > > +} > > > > --00000000000094af6605fc69df33 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Hi WeiWei Li,


When= the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml` for the fir= st time with the correct `base_reg` value.


code flow := =C2=A0

riscv_cpu_realize

=E2=86=92 riscv_cpu_= register_gdb_regs_for_features

=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=E2=86=92 riscv_gen_dynamic_csr_xml


The functionali= ty of `cpu->dyn_csr_base_reg` is to record the `base_reg` from

`riscv_cpu_regi= ster_gdb_regs_for_features`.


When we try to refresh the = dynamic CSRs xml, we will call the function `riscv_gen_dynamic_csr_xml`

for the second time, and then we can give the correct `base_reg= ` value to the function

`riscv_gen_dynamic_csr_xml`, because= we've record this value in the `cpu->dyn_csr_base_reg`.


B= est Regards,

Tommy



On Wed, May 24, 2023 at 10:10=E2=80=AFAM Weiwei Li &l= t;liweiwei@iscas.ac.cn> wrot= e:

On 2023/5/24 09:59, Tommy Wu wrote:
> Hi=C2=A0Weiwei Li,
>
> `dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml`
> We can initialize this variable when the cpu is realized.
I didn't find this initialization in following code.
> And used this variable in `riscv_refresh_dynamic_csr_xml`.

That's my question. In riscv_refresh_dynamic_csr_xml() ,
cpu->dyn_csr_base_reg is passed to riscv_gen_dynamic_csr_xml() as base_r= eg.

And then base_reg is assigned to cpu->dyn_csr_base_reg again in it. So <= br> it's unchanged in this progress.

Another question is=C2=A0 dyn_csr_base_reg seems have no additional functio= n
currently.

Regards,

Weiwei Li

>
> Best=C2=A0regards,
> Tommy
>
>
> On Tue, May 23, 2023 at 10:38=E2=80=AFPM Weiwei Li <liweiwei@iscas.ac.cn> wro= te:
>
>
>=C2=A0 =C2=A0 =C2=A0On 2023/5/23 19:44, Tommy Wu wrote:
>=C2=A0 =C2=A0 =C2=A0> When we change the cpu extension state after t= he cpu is
>=C2=A0 =C2=A0 =C2=A0> realized, we cannot print the value of some CS= Rs in the remote
>=C2=A0 =C2=A0 =C2=A0> gdb debugger. The root cause is that the dynam= ic CSR xml is
>=C2=A0 =C2=A0 =C2=A0> generated when the cpu is realized.
>=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> This patch add a function to refresh the dynam= ic CSR xml after
>=C2=A0 =C2=A0 =C2=A0> the cpu is realized.
>=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
>=C2=A0 =C2=A0 =C2=A0> Reviewed-by: Frank Chang <frank.chang@sifive.com> >=C2=A0 =C2=A0 =C2=A0> ---
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 = =C2=A0|=C2=A0 2 ++
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0target/riscv/gdbstub.c | 12 ++++++= ++++++
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A02 files changed, 14 insertions(+)<= br> >=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> diff --git a/target/riscv/cpu.h b/target/riscv= /cpu.h
>=C2=A0 =C2=A0 =C2=A0> index de7e43126a..dc8e592275 100644
>=C2=A0 =C2=A0 =C2=A0> --- a/target/riscv/cpu.h
>=C2=A0 =C2=A0 =C2=A0> +++ b/target/riscv/cpu.h
>=C2=A0 =C2=A0 =C2=A0> @@ -494,6 +494,7 @@ struct ArchCPU {
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0CPUNegativeOffsetSta= te neg;
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0CPURISCVState env; >=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 int dyn_csr_base_reg;
>
>=C2=A0 =C2=A0 =C2=A0dyn_csr_base_reg=C2=A0 seems have no additional eff= ect on the function.
>
>=C2=A0 =C2=A0 =C2=A0And It remains unmodified in following
>=C2=A0 =C2=A0 =C2=A0riscv_refresh_dynamic_csr_xml().
>
>=C2=A0 =C2=A0 =C2=A0Regards,
>
>=C2=A0 =C2=A0 =C2=A0Weiwei Li
>
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0char *dyn_csr_xml; >=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0char *dyn_vreg_xml;<= br> >=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int= csrno,
>=C2=A0 =C2=A0 =C2=A0riscv_csr_operations *ops);
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0void riscv_set_csr_ops(int csrno, = riscv_csr_operations *ops);
>=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0void riscv_cpu_register_gdb_regs_f= or_features(CPUState *cs);
>=C2=A0 =C2=A0 =C2=A0> +void riscv_refresh_dynamic_csr_xml(CPUState *= cs);
>=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0uint8_t satp_mode_max_from_map(uin= t32_t map);
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0const char *satp_mode_str(uint8_t = satp_mode, bool is_32_bit);
>=C2=A0 =C2=A0 =C2=A0> diff --git a/target/riscv/gdbstub.c b/target/r= iscv/gdbstub.c
>=C2=A0 =C2=A0 =C2=A0> index 524bede865..9e97ee2c35 100644
>=C2=A0 =C2=A0 =C2=A0> --- a/target/riscv/gdbstub.c
>=C2=A0 =C2=A0 =C2=A0> +++ b/target/riscv/gdbstub.c
>=C2=A0 =C2=A0 =C2=A0> @@ -230,6 +230,8 @@ static int
>=C2=A0 =C2=A0 =C2=A0riscv_gen_dynamic_csr_xml(CPUState *cs, int base_re= g)
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bitsiz= e =3D 64;
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0>
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 cpu->dyn_csr_base_reg =3D ba= se_reg;
>=C2=A0 =C2=A0 =C2=A0> +
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0g_string_printf(s, &= quot;<?xml version=3D\"1.0\"?>");
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0g_string_append_prin= tf(s, "<!DOCTYPE feature SYSTEM
>=C2=A0 =C2=A0 =C2=A0\"gdb-target.dtd\">");
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0g_string_append_prin= tf(s, "<feature
>=C2=A0 =C2=A0 =C2=A0name=3D\"org.gnu.gdb.riscv.csr\">"= ;);
>=C2=A0 =C2=A0 =C2=A0> @@ -349,3 +351,13 @@ void
>=C2=A0 =C2=A0 =C2=A0riscv_cpu_register_gdb_regs_for_features(CPUState *= cs)
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 "riscv-csr.xml", 0);
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0> +
>=C2=A0 =C2=A0 =C2=A0> +void riscv_refresh_dynamic_csr_xml(CPUState *= cs)
>=C2=A0 =C2=A0 =C2=A0> +{
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D RISCV_CPU(cs)= ;
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 if (!cpu->dyn_csr_xml) {
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reac= hed();
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 g_free(cpu->dyn_csr_xml); >=C2=A0 =C2=A0 =C2=A0> +=C2=A0 =C2=A0 riscv_gen_dynamic_csr_xml(cs, c= pu->dyn_csr_base_reg);
>=C2=A0 =C2=A0 =C2=A0> +}
>

--00000000000094af6605fc69df33--