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To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=tommy.wu@sifive.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jun 12, 2023 at 1:04=E2=80=AFPM Alistair Francis wrote: > > On Thu, Jun 8, 2023 at 5:25=E2=80=AFPM Tommy Wu wro= te: > > > > Signed-off-by: Frank Chang > > Signed-off-by: Tommy Wu > > --- > > hw/riscv/riscv_hart.c | 21 +++++++++++++++++++++ > > include/hw/riscv/riscv_hart.h | 4 ++++ > > target/riscv/cpu.c | 13 +++++++++++++ > > target/riscv/cpu.h | 7 +++++++ > > target/riscv/cpu_bits.h | 12 ++++++++++++ > > target/riscv/cpu_helper.c | 24 ++++++++++++++++++++++++ > > 6 files changed, 81 insertions(+) > > > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > > index 613ea2aaa0..eac18f8c29 100644 > > --- a/hw/riscv/riscv_hart.c > > +++ b/hw/riscv/riscv_hart.c > > @@ -33,6 +33,12 @@ static Property riscv_harts_props[] =3D { > > DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), > > DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, > > DEFAULT_RSTVEC), > > + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, > > + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, > > + uint64_t), > > + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, > > + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64= , > > + uint64_t), > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > @@ -47,6 +53,21 @@ static bool riscv_hart_realize(RISCVHartArrayState *= s, int idx, > > { > > object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu= _type); > > qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetv= ec); > > + > > + if (s->harts[idx].cfg.ext_smrnmi) { > > + if (s->rnmi_irqvec) { > > + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), > > + "rnmi-interrupt-vector", > > + s->rnmi_irqvec[idx]); > > + } > > + > > + if (s->rnmi_excpvec) { > > + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), > > + "rnmi-exception-vector", > > + s->rnmi_excpvec[idx]); > > + } > > + } > > + > > s->harts[idx].env.mhartid =3D s->hartid_base + idx; > > qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); > > return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); > > diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_har= t.h > > index bbc21cdc9a..99c0ac5009 100644 > > --- a/include/hw/riscv/riscv_hart.h > > +++ b/include/hw/riscv/riscv_hart.h > > @@ -38,6 +38,10 @@ struct RISCVHartArrayState { > > uint32_t hartid_base; > > char *cpu_type; > > uint64_t resetvec; > > + uint32_t num_rnmi_irqvec; > > + uint64_t *rnmi_irqvec; > > + uint32_t num_rnmi_excpvec; > > + uint64_t *rnmi_excpvec; > > RISCVCPU *harts; > > }; > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index db0875fb43..c8dc0eaa87 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D { > > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), > > The extension should be added after the implementation, so this patch > should be the last patch. > > Alistair Thanks for the suggestion, I'll move this patch to the last patch. > > > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > > @@ -1404,6 +1405,11 @@ static void riscv_cpu_set_irq(void *opaque, int = irq, int level) > > g_assert_not_reached(); > > } > > } > > + > > +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) > > +{ > > + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); > > +} > > #endif /* CONFIG_USER_ONLY */ > > > > static void riscv_cpu_init(Object *obj) > > @@ -1420,6 +1426,8 @@ static void riscv_cpu_init(Object *obj) > > #ifndef CONFIG_USER_ONLY > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, > > IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); > > + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, > > + "riscv.cpu.rnmi", RNMI_MAX); > > #endif /* CONFIG_USER_ONLY */ > > } > > > > @@ -1600,6 +1608,7 @@ static Property riscv_cpu_extensions[] =3D { > > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), > > DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), > > + DEFINE_PROP_BOOL("x-smrnmi", RISCVCPU, cfg.ext_smrnmi, false), > > > > DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), > > DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), > > @@ -1644,6 +1653,10 @@ static Property riscv_cpu_properties[] =3D { > > > > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, fal= se), > > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, fal= se), > > + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irq= vec, > > + DEFAULT_RNMI_IRQVEC), > > + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_exc= pvec, > > + DEFAULT_RNMI_EXCPVEC), > > > > /* > > * write_misa() is marked as experimental for now so mark > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index de7e43126a..6c14b93cb5 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -366,6 +366,11 @@ struct CPUArchState { > > uint64_t kvm_timer_compare; > > uint64_t kvm_timer_state; > > uint64_t kvm_timer_frequency; > > + > > + /* RNMI */ > > + target_ulong rnmip; > > + uint64_t rnmi_irqvec; > > + uint64_t rnmi_excpvec; > > }; > > > > /* > > @@ -436,6 +441,7 @@ struct RISCVCPUConfig { > > bool ext_smaia; > > bool ext_ssaia; > > bool ext_sscofpmf; > > + bool ext_smrnmi; > > bool rvv_ta_all_1s; > > bool rvv_ma_all_1s; > > > > @@ -562,6 +568,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *= env); > > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); > > uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, > > uint64_t value); > > +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); > > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip va= lue */ > > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *= ), > > void *arg); > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 59f0ffd9e1..7cb43b88f3 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -659,6 +659,12 @@ typedef enum { > > /* Default Reset Vector adress */ > > #define DEFAULT_RSTVEC 0x1000 > > > > +/* Default RNMI Interrupt Vector address */ > > +#define DEFAULT_RNMI_IRQVEC 0x0 > > + > > +/* Default RNMI Exception Vector address */ > > +#define DEFAULT_RNMI_EXCPVEC 0x0 > > + > > /* Exception causes */ > > typedef enum RISCVException { > > RISCV_EXCP_NONE =3D -1, /* sentinel value */ > > @@ -705,6 +711,9 @@ typedef enum RISCVException { > > #define IRQ_LOCAL_MAX 16 > > #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) > > > > +/* RNMI causes */ > > +#define RNMI_MAX 16 > > + > > /* mip masks */ > > #define MIP_USIP (1 << IRQ_U_SOFT) > > #define MIP_SSIP (1 << IRQ_S_SOFT) > > @@ -896,6 +905,9 @@ typedef enum RISCVException { > > #define MHPMEVENT_IDX_MASK 0xFFFFF > > #define MHPMEVENT_SSCOF_RESVD 16 > > > > +/* RISC-V-specific interrupt pending bits. */ > > +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 > > + > > /* JVT CSR bits */ > > #define JVT_MODE 0x3F > > #define JVT_BASE (~0x3F) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 56381aaf26..da477b6c99 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -636,6 +636,30 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, = uint64_t mask, > > return old; > > } > > > > +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) > > +{ > > + CPURISCVState *env =3D &cpu->env; > > + CPUState *cs =3D CPU(cpu); > > + bool release_lock =3D false; > > + > > + if (!qemu_mutex_iothread_locked()) { > > + release_lock =3D true; > > + qemu_mutex_lock_iothread(); > > + } > > + > > + if (level) { > > + env->rnmip |=3D 1 << irq; > > + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); > > + } else { > > + env->rnmip &=3D ~(1 << irq); > > + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); > > + } > > + > > + if (release_lock) { > > + qemu_mutex_unlock_iothread(); > > + } > > +} > > + > > void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *= ), > > void *arg) > > { > > -- > > 2.31.1 > > > >