Re: [PATCH v2] target/riscv: Expose "priv" register for GDB

[Jonathan Behrens <jonathan@fintelia.io>]

On Mon, Oct 7, 2019 at 2:36 PM Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, Oct 4, 2019 at 8:18 AM Jonathan Behrens <jonathan@fintelia.io> wrote:
> > @@ -296,6 +302,14 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> >      } else if (n == 32) {
> >          env->pc = ldtul_p(mem_buf);
> >          return sizeof(target_ulong);
> > +    } else if (n == 33) {
> > +#ifndef CONFIG_USER_ONLY
> > +        env->priv = ldtul_p(mem_buf) & 0x3;
> > +        if (env->priv == PRV_H) {
> > +            env->priv = PRV_S;
> > +        }
>
> Why have this? There is no PRV_H so we should never be in that privilege mode.
>
> Alistair

This is hopefully more clear in the next version, but the idea is that
since GDB can try to set the privilege mode to *any* value this
function needs to make sure that it isn't set to something unsupported
like PRV_H.

Jonathan