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[209.85.222.169]) by smtp.gmail.com with ESMTPSA id t29sm6890498qtt.42.2019.06.23.23.42.53 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Sun, 23 Jun 2019 23:42:54 -0700 (PDT) Received: by mail-qk1-f169.google.com with SMTP id x18so8898449qkn.13 for ; Sun, 23 Jun 2019 23:42:53 -0700 (PDT) X-Received: by 2002:a05:620a:1106:: with SMTP id o6mr101869223qkk.272.1561358573519; Sun, 23 Jun 2019 23:42:53 -0700 (PDT) MIME-Version: 1.0 References: <20190616191900.GH61734@hippo.sing.id.au> <41ef5fbf-f438-e60a-2fba-a72e3ad422f9@linaro.org> In-Reply-To: <41ef5fbf-f438-e60a-2fba-a72e3ad422f9@linaro.org> From: Palmer Dabbelt Date: Sun, 23 Jun 2019 23:42:42 -0700 X-Gmail-Original-Message-ID: Message-ID: To: Richard Henderson X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlos Eduardo de Paula , "open list:RISC-V" , Palmer Dabbelt , qemu-devel@nongnu.org, Joel Sing , Alistair Francis , Marco Peereboom Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jun 17, 2019 at 4:53 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 6/16/19 12:19 PM, Joel Sing wrote: > > + /* > > + * Clear the load reservation, since an SC must fail if there is > > + * an SC to any address, in between an LR and SC pair. > > + */ > > + tcg_gen_movi_tl(load_res, 0); > > + > > gen_set_label(l2); > > This clear needs to be moved down below label l2. > Otherwise, with lr / sc / sc, the second sc could succeed in error. > > FWIW, other targets have used -1 as the "invalid" load reservation, since > the > architecture does not require address 0 to be unmapped. This should be > quite > visible in M-mode with paging disabled and ram at offset 0. Often, other > targets require alignment for the lr/sc address, though I don't see that > for riscv. > > > r~ > Joel: can you submit this with a "Signed-off-by" line? There's only a week until the soft freeze, and I'd really like this in if possible. It'd be great if you could fix up the other issues, but I can't even do that myself without a SOB.