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[209.85.221.182]) by smtp.gmail.com with ESMTPSA id w6-20020ab067c6000000b0036280b488c7sm4140861uar.16.2022.05.04.02.53.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 May 2022 02:53:52 -0700 (PDT) Received: by mail-vk1-f182.google.com with SMTP id o132so346911vko.11; Wed, 04 May 2022 02:53:52 -0700 (PDT) X-Received: by 2002:a1f:a3d7:0:b0:349:6b56:a90 with SMTP id m206-20020a1fa3d7000000b003496b560a90mr6764668vke.12.1651658031779; Wed, 04 May 2022 02:53:51 -0700 (PDT) MIME-Version: 1.0 References: <20220429153431.308829-1-apatel@ventanamicro.com> <20220429153431.308829-3-apatel@ventanamicro.com> In-Reply-To: <20220429153431.308829-3-apatel@ventanamicro.com> From: Frank Chang Date: Wed, 4 May 2022 17:53:41 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher To: Anup Patel Cc: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Anup Patel , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Atish Patra Content-Type: multipart/alternative; boundary="000000000000465b2205de2c9ae9" Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=frank.chang@sifive.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000465b2205de2c9ae9 Content-Type: text/plain; charset="UTF-8" Hi Anup, I found that Atish has already submitted a patch to implement the mcountinhibit CSR: https://www.mail-archive.com/qemu-devel@nongnu.org/msg879349.html Regards, Frank Chang On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote: > The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For > implementation that don't want to implement can simply have a dummy > mcountinhibit which always zero. > > Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in > the CSR ops.") > Signed-off-by: Anup Patel > --- > target/riscv/cpu_bits.h | 3 +++ > target/riscv/csr.c | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 4d04b20d06..4a55c6a709 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -159,6 +159,9 @@ > #define CSR_MTVEC 0x305 > #define CSR_MCOUNTEREN 0x306 > > +/* Machine Counter Setup */ > +#define CSR_MCOUNTINHIBIT 0x320 > + > /* 32-bit only */ > #define CSR_MSTATUSH 0x310 > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 2bf0a97196..e144ce7135 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie > }, > [CSR_MTVEC] = { "mtvec", any, read_mtvec, > write_mtvec }, > [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, > write_mcounteren }, > + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore, > + .min_priv_ver = > PRIV_VERSION_1_11_0 }, > > [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, > write_mstatush }, > > -- > 2.34.1 > > > --000000000000465b2205de2c9ae9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Anup,

I found that Atish has already= submitted a patch to implement the mcountinhibit CSR:

Regards,
Frank Chang

On Fri, Apr 29, 2022= at 11:44 PM Anup Patel <apat= el@ventanamicro.com> wrote:
The mcountinhibit CSR is mandatory for priv spec v1.11 o= r higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.

Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field = in
the CSR ops.")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
=C2=A0target/riscv/cpu_bits.h | 3 +++
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 2 ++
=C2=A02 files changed, 5 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4d04b20d06..4a55c6a709 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -159,6 +159,9 @@
=C2=A0#define CSR_MTVEC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x305
=C2=A0#define CSR_MCOUNTEREN=C2=A0 =C2=A0 =C2=A0 0x306

+/* Machine Counter Setup */
+#define CSR_MCOUNTINHIBIT=C2=A0 =C2=A00x320
+
=C2=A0/* 32-bit only */
=C2=A0#define CSR_MSTATUSH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x310

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 2bf0a97196..e144ce7135 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =C2=A0 =C2=A0 =C2=A0[CSR_MIE]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D { "= mie",=C2=A0 =C2=A0 =C2=A0 =C2=A0 any,=C2=A0 =C2=A0NULL,=C2=A0 =C2=A0 N= ULL,=C2=A0 =C2=A0 rmw_mie=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0},
=C2=A0 =C2=A0 =C2=A0[CSR_MTVEC]=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D { "mtvec= ",=C2=A0 =C2=A0 =C2=A0 any,=C2=A0 =C2=A0read_mtvec,=C2=A0 =C2=A0 =C2= =A0 =C2=A0write_mtvec=C2=A0 =C2=A0 =C2=A0 =C2=A0},
=C2=A0 =C2=A0 =C2=A0[CSR_MCOUNTEREN]=C2=A0 =3D { "mcounteren", an= y,=C2=A0 =C2=A0read_mcounteren,=C2=A0 write_mcounteren=C2=A0 },
+=C2=A0 =C2=A0 [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, re= ad_zero, write_ignore,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0.min_priv_ver =3D PRIV_VERSION_1_11_0 },

=C2=A0 =C2=A0 =C2=A0[CSR_MSTATUSH]=C2=A0 =C2=A0 =3D { "mstatush",= =C2=A0 =C2=A0any32, read_mstatush,=C2=A0 =C2=A0 write_mstatush=C2=A0 =C2=A0= },

--
2.34.1


--000000000000465b2205de2c9ae9--