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[209.85.208.176]) by smtp.gmail.com with ESMTPSA id l26-20020ac2555a000000b004cb45148027sm1269021lfk.203.2023.02.23.02.10.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Feb 2023 02:10:20 -0800 (PST) Received: by mail-lj1-f176.google.com with SMTP id y14so3190093ljq.4; Thu, 23 Feb 2023 02:10:20 -0800 (PST) X-Received: by 2002:a2e:a497:0:b0:295:945d:b381 with SMTP id h23-20020a2ea497000000b00295945db381mr2051354lji.7.1677147020141; Thu, 23 Feb 2023 02:10:20 -0800 (PST) MIME-Version: 1.0 References: <20230221091009.36545-1-liweiwei@iscas.ac.cn> In-Reply-To: <20230221091009.36545-1-liweiwei@iscas.ac.cn> From: Frank Chang Date: Thu, 23 Feb 2023 18:10:08 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] target/riscv: Add support for Zicond extension To: Weiwei Li Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com Content-Type: multipart/alternative; boundary="0000000000005f2ac105f55b3873" Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=frank.chang@sifive.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000005f2ac105f55b3873 Content-Type: text/plain; charset="UTF-8" Reviewed-by: Frank Chang On Tue, Feb 21, 2023 at 5:10 PM Weiwei Li wrote: > The spec can be found in https://github.com/riscv/riscv-zicond. > Two instructions are added: > - czero.eqz: Moves zero to a register rd, if the condition rs2 is > equal to zero, otherwise moves rs1 to rd. > - czero.nez: Moves zero to a register rd, if the condition rs2 is > nonzero, otherwise moves rs1 to rd. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn32.decode | 4 ++ > target/riscv/insn_trans/trans_rvzicond.c.inc | 49 ++++++++++++++++++++ > target/riscv/translate.c | 1 + > 5 files changed, 57 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzicond.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0dd2f0c753..80b92930ae 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -74,6 +74,7 @@ struct isa_ext_data { > static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), > ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), > + ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, > ext_zihintpause), > @@ -1143,6 +1144,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, > cfg.ext_XVentanaCondOps, false), > > /* These are experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7128438d8e..81b7c92e7a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -447,6 +447,7 @@ struct RISCVCPUConfig { > bool ext_zkt; > bool ext_ifencei; > bool ext_icsr; > + bool ext_zicond; > bool ext_zihintpause; > bool ext_smstateen; > bool ext_sstc; > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index b7e7613ea2..fb537e922e 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -890,3 +890,7 @@ sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2 > # *** RV32 Zksed Standard Extension *** > sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes > sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes > + > +# *** RV32 Zicond Standard Extension *** > +czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r > +czero_nez 0000111 ..... ..... 111 ..... 0110011 @r > diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc > b/target/riscv/insn_trans/trans_rvzicond.c.inc > new file mode 100644 > index 0000000000..645260164e > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvzicond.c.inc > @@ -0,0 +1,49 @@ > +/* > + * RISC-V translation routines for the Zicond Standard Extension. > + * > + * Copyright (c) 2020-2023 PLCT Lab > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > for > + * more details. > + * > + * You should have received a copy of the GNU General Public License > along with > + * this program. If not, see . > + */ > + > +#define REQUIRE_ZICOND(ctx) do { \ > + if (!ctx->cfg_ptr->ext_zicond) { \ > + return false; \ > + } \ > +} while (0) > + > +static bool trans_czero_eqz(DisasContext *ctx, arg_czero_eqz *a) > +{ > + REQUIRE_ZICOND(ctx); > + > + TCGv dest = dest_gpr(ctx, a->rd); > + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); > + > + tcg_gen_movcond_tl(TCG_COND_EQ, dest, src2, ctx->zero, ctx->zero, > src1); > + gen_set_gpr(ctx, a->rd, dest); > + return true; > +} > + > +static bool trans_czero_nez(DisasContext *ctx, arg_czero_nez *a) > +{ > + REQUIRE_ZICOND(ctx); > + > + TCGv dest = dest_gpr(ctx, a->rd); > + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); > + > + tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, ctx->zero, ctx->zero, > src1); > + gen_set_gpr(ctx, a->rd, dest); > + return true; > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 772f9d7973..6e65c6afca 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1103,6 +1103,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > #include "insn_trans/trans_rvh.c.inc" > #include "insn_trans/trans_rvv.c.inc" > #include "insn_trans/trans_rvb.c.inc" > +#include "insn_trans/trans_rvzicond.c.inc" > #include "insn_trans/trans_rvzawrs.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_rvk.c.inc" > -- > 2.25.1 > > > --0000000000005f2ac105f55b3873 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Frank Chang <frank.chang@sifive.com>

On Tue, Feb 21, 2023 at 5:10 PM = Weiwei Li <liweiwei@iscas.ac.cn<= /a>> wrote:
T= he spec can be found in https://github.com/riscv/riscv-zicond.
Two instructions are added:
=C2=A0- czero.eqz: Moves zero to a register rd, if the condition rs2 is
=C2=A0 =C2=A0equal to zero, otherwise moves rs1 to rd.
=C2=A0- czero.nez: Moves zero to a register rd, if the condition rs2 is
=C2=A0 =C2=A0nonzero, otherwise moves rs1 to rd.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
=C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 +
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
=C2=A0target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 4 ++
=C2=A0target/riscv/insn_trans/trans_rvzicond.c.inc | 49 +++++++++++++++++++= +
=C2=A0target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
=C2=A05 files changed, 57 insertions(+)
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzicond.c.inc

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..80b92930ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -74,6 +74,7 @@ struct isa_ext_data {
=C2=A0static const struct isa_ext_data isa_edata_arr[] =3D {
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h= ),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v= ),
+=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zi= cond),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ex= t_icsr),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0,= ext_ifencei),
=C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10= _0, ext_zihintpause),
@@ -1143,6 +1144,7 @@ static Property riscv_cpu_extensions[] =3D {
=C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("xventanacondops", RISCVCPU,= cfg.ext_XVentanaCondOps, false),

=C2=A0 =C2=A0 =C2=A0/* These are experimental so mark with 'x-' */<= br> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zic= ond, false),
=C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, = false),
=C2=A0 =C2=A0 =C2=A0/* ePMP 0.9.3 */
=C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp= , false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..81b7c92e7a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -447,6 +447,7 @@ struct RISCVCPUConfig {
=C2=A0 =C2=A0 =C2=A0bool ext_zkt;
=C2=A0 =C2=A0 =C2=A0bool ext_ifencei;
=C2=A0 =C2=A0 =C2=A0bool ext_icsr;
+=C2=A0 =C2=A0 bool ext_zicond;
=C2=A0 =C2=A0 =C2=A0bool ext_zihintpause;
=C2=A0 =C2=A0 =C2=A0bool ext_smstateen;
=C2=A0 =C2=A0 =C2=A0bool ext_sstc;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b7e7613ea2..fb537e922e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -890,3 +890,7 @@ sm3p1=C2=A0 =C2=A0 =C2=A0 =C2=A000 01000 01001 ..... 00= 1 ..... 0010011 @r2
=C2=A0# *** RV32 Zksed Standard Extension ***
=C2=A0sm4ed=C2=A0 =C2=A0 =C2=A0 =C2=A0.. 11000 ..... ..... 000 ..... 011001= 1 @k_aes
=C2=A0sm4ks=C2=A0 =C2=A0 =C2=A0 =C2=A0.. 11010 ..... ..... 000 ..... 011001= 1 @k_aes
+
+# *** RV32 Zicond Standard Extension ***
+czero_eqz=C2=A0 =C2=A00000111=C2=A0 ..... ..... 101 ..... 0110011 @r
+czero_nez=C2=A0 =C2=A00000111=C2=A0 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/in= sn_trans/trans_rvzicond.c.inc
new file mode 100644
index 0000000000..645260164e
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzicond.c.inc
@@ -0,0 +1,49 @@
+/*
+ * RISC-V translation routines for the Zicond Standard Extension.
+ *
+ * Copyright (c) 2020-2023 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it=
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT<= br> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public Lice= nse for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along= with
+ * this program.=C2=A0 If not, see <http://www.gnu.org/licenses/= >.
+ */
+
+#define REQUIRE_ZICOND(ctx) do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 if (!ctx->cfg_ptr->ext_zicond) {=C2=A0 =C2=A0 =C2=A0 \=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
+=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\<= br> +} while (0)
+
+static bool trans_czero_eqz(DisasContext *ctx, arg_czero_eqz *a)
+{
+=C2=A0 =C2=A0 REQUIRE_ZICOND(ctx);
+
+=C2=A0 =C2=A0 TCGv dest =3D dest_gpr(ctx, a->rd);
+=C2=A0 =C2=A0 TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE);
+=C2=A0 =C2=A0 TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE);
+
+=C2=A0 =C2=A0 tcg_gen_movcond_tl(TCG_COND_EQ, dest, src2, ctx->zero, ct= x->zero, src1);
+=C2=A0 =C2=A0 gen_set_gpr(ctx, a->rd, dest);
+=C2=A0 =C2=A0 return true;
+}
+
+static bool trans_czero_nez(DisasContext *ctx, arg_czero_nez *a)
+{
+=C2=A0 =C2=A0 REQUIRE_ZICOND(ctx);
+
+=C2=A0 =C2=A0 TCGv dest =3D dest_gpr(ctx, a->rd);
+=C2=A0 =C2=A0 TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE);
+=C2=A0 =C2=A0 TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE);
+
+=C2=A0 =C2=A0 tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, ctx->zero, ct= x->zero, src1);
+=C2=A0 =C2=A0 gen_set_gpr(ctx, a->rd, dest);
+=C2=A0 =C2=A0 return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 772f9d7973..6e65c6afca 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1103,6 +1103,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc)
=C2=A0#include "insn_trans/trans_rvh.c.inc"
=C2=A0#include "insn_trans/trans_rvv.c.inc"
=C2=A0#include "insn_trans/trans_rvb.c.inc"
+#include "insn_trans/trans_rvzicond.c.inc"
=C2=A0#include "insn_trans/trans_rvzawrs.c.inc"
=C2=A0#include "insn_trans/trans_rvzfh.c.inc"
=C2=A0#include "insn_trans/trans_rvk.c.inc"
--
2.25.1


--0000000000005f2ac105f55b3873--