From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5732C433F5 for ; Thu, 17 Mar 2022 10:53:26 +0000 (UTC) Received: from localhost ([::1]:45044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nUnkz-0006Nh-KH for qemu-devel@archiver.kernel.org; Thu, 17 Mar 2022 06:53:25 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nUniH-0003Vj-1U for qemu-devel@nongnu.org; Thu, 17 Mar 2022 06:50:37 -0400 Received: from [2607:f8b0:4864:20::102e] (port=51168 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nUniE-0002FU-8N for qemu-devel@nongnu.org; Thu, 17 Mar 2022 06:50:35 -0400 Received: by mail-pj1-x102e.google.com with SMTP id m22so4568033pja.0 for ; Thu, 17 Mar 2022 03:50:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8dsGzh7OzwqMzf0UX0mIcrVi62Va0oZfgy9O0WF9Pbc=; b=mrC3A0cJxz6MP00betJXO0JsfHk2qgmDVfi7fIIvHhZcRsG2T9ku7XtqJ6SaSL4CJS xGhCNN7RxohBpDEzAjviqa5AWd2FOzY/S0+yutnd7AZT6eZ9bF1ro88xpZl1RuywcHXL WQSqI/smxaJQqrqmjKebm/ajibiTP0FwTIOwCdqzGHg0t2uSCdYKngNYGqbhzqOX93Jk JP/YfM/CXkhF61717iQHW7eoN9E8vSUBhGyhiVf3M+IDbWNRMkL8QjGcFbrbBRuJx2Is rlzzsPUKOULbPYO6Kps82+VuhHXWdCGT4i8RGJcFAE7AK3Nl5WFdqwl139nCLOjl9oxA DnVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8dsGzh7OzwqMzf0UX0mIcrVi62Va0oZfgy9O0WF9Pbc=; b=PbFolrG3EITJ7LsYXBKp8ns1vQx2EoP7RxmVP0p57WN66g3EtnYTHC3aOldsj2ih6P yzkmhwDLiuo/WPy2qf79SlX3dTChMUvoQtuQWWX41COloWuzoJ86M0qUzKL8Vcuznbj2 lVL7n1h8BWX1kdXYYa7JVEpjwM+hOCm4LQvYrcSH2/E3yTSJSXuhNVEshe1WtY+UslQH CTvSnAIdcULz/ANrng3b/hRQQPYsa1N2K0r6FiphOf+O3dfrMKaFDDqkiKxyb+RP/d5z s7wjdivFhBoj42H07THvo8eliLHa+axfDfxkrqUiBJmO2UV4HFvxP9iguUC/QNGMbzu4 ABjg== X-Gm-Message-State: AOAM5301wSN0xk4ZamZZIM8CrXkWsy3Xa7iHw9WpphwJZcmi1O0dJ8f5 Vhe2OH7aBtpuuNPRYIdnAUTcZ+i7bV5JLDZd X-Google-Smtp-Source: ABdhPJyFYj3el022xodgh4w85koj8PXoOncKahSpEkOA8pG8kHTds641Wd3YH6VKnwqEURhACl2sJg== X-Received: by 2002:a17:902:d2cc:b0:152:fda8:f3ff with SMTP id n12-20020a170902d2cc00b00152fda8f3ffmr4461664plc.92.1647514232456; Thu, 17 Mar 2022 03:50:32 -0700 (PDT) Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com. [209.85.210.174]) by smtp.gmail.com with ESMTPSA id c7-20020aa78e07000000b004f6e4d8ccc8sm6264521pfr.163.2022.03.17.03.50.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Mar 2022 03:50:31 -0700 (PDT) Received: by mail-pf1-f174.google.com with SMTP id p5so368264pfo.5; Thu, 17 Mar 2022 03:50:30 -0700 (PDT) X-Received: by 2002:a05:6a00:1304:b0:4e1:2338:f11e with SMTP id j4-20020a056a00130400b004e12338f11emr4366547pfu.24.1647514230019; Thu, 17 Mar 2022 03:50:30 -0700 (PDT) MIME-Version: 1.0 References: <20220316175759.821785-1-atishp@rivosinc.com> In-Reply-To: <20220316175759.821785-1-atishp@rivosinc.com> From: Frank Chang Date: Thu, 17 Mar 2022 18:50:19 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree To: Atish Patra Content-Type: multipart/alternative; boundary="000000000000715d3105da67cce9" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Heiko Stubner , Anup Patel , Bin Meng , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000715d3105da67cce9 Content-Type: text/plain; charset="UTF-8" On Thu, Mar 17, 2022 at 1:58 AM Atish Patra wrote: > The Linux kernel parses the ISA extensions from "riscv,isa" DT > property. It used to parse only the single letter base extensions > until now. A generic ISA extension parsing framework was proposed[1] > recently that can parse multi-letter ISA extensions as well. > > Generate the extended ISA string by appending the available ISA extensions > to the "riscv,isa" string if it is enabled so that kernel can process it. > > [1] https://lkml.org/lkml/2022/2/15/263 > > Reviewed-by: Anup Patel > Reviewed-by: Alistair Francis > Suggested-by: Heiko Stubner > Signed-off-by: Atish Patra > --- > Changes from v5->v6: > 1. Improved commit message. > 2. Fixed a typo for Zfh. > > Changes from v4->v5: > 1. Fixed the order of Zxx extensions. > 2. Added a comment clearly describing the rules of extension order. > > Changes from v3->v4: > 1. Fixed the order of the extension names. > 2. Added all the available ISA extensions in Qemu. > > Changes from v2->v3: > 1. Used g_strconcat to replace snprintf & a max isa string length as > suggested by Anup. > 2. I have not included the Tested-by Tag from Heiko because the > implementation changed from v2 to v3. > > Changes from v1->v2: > 1. Improved the code redability by using arrays instead of individual check > --- > target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ddda4906ffb7..937ccdda997b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -34,6 +34,11 @@ > > /* RISC-V CPU definitions */ > > +struct isa_ext_data { > + const char *name; > + bool enabled; > Nit: Should be 4 spaces indent. Regards, Frank Chang > +}; > + > static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; > > const char * const riscv_int_regnames[] = { > @@ -898,6 +903,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void > *data) > device_class_set_props(dc, riscv_cpu_properties); > } > > +#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} > + > +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int > max_str_len) > +{ > + char *old = *isa_str; > + char *new = *isa_str; > + int i; > + > + /** > + * Here are the ordering rules of extension naming defined by RISC-V > + * specification : > + * 1. All extensions should be separated from from other multi-letter > + * extensions by an underscore. > + * 2. The first letter following the 'Z' conventionally indicates the > most > + * closely related alphabetical extension category, > IMAFDQLCBKJTPVH. > + * If multiple 'Z' extensions are named, they should be ordered > first > + * by category, then alphabetically within a category. > + * 3. Standard supervisor-level extensions (starts with 'S') should be > + * listed after standard unprivileged extensions. If multiple > + * supervisor-level extensions are listed, they should be ordered > + * alphabetically. > + * 4. Non-standard extensions (starts with 'X') must be listed after > all > + * standard extensions. They must be separated from other > multi-letter > + * extensions by an underscore. > + */ > + struct isa_ext_data isa_edata_arr[] = { > + ISA_EDATA_ENTRY(zfh, ext_zfh), > + ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > + ISA_EDATA_ENTRY(zfinx, ext_zfinx), > + ISA_EDATA_ENTRY(zdinx, ext_zdinx), > + ISA_EDATA_ENTRY(zba, ext_zba), > + ISA_EDATA_ENTRY(zbb, ext_zbb), > + ISA_EDATA_ENTRY(zbc, ext_zbc), > + ISA_EDATA_ENTRY(zbs, ext_zbs), > + ISA_EDATA_ENTRY(zve32f, ext_zve32f), > + ISA_EDATA_ENTRY(zve64f, ext_zve64f), > + ISA_EDATA_ENTRY(zhinx, ext_zhinx), > + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), > + ISA_EDATA_ENTRY(svinval, ext_svinval), > + ISA_EDATA_ENTRY(svnapot, ext_svnapot), > + ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), > + }; > + > + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > + if (isa_edata_arr[i].enabled) { > + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > + g_free(old); > + old = new; > + } > + } > + > + *isa_str = new; > +} > + > char *riscv_isa_string(RISCVCPU *cpu) > { > int i; > @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu) > } > } > *p = '\0'; > + riscv_isa_string_ext(cpu, &isa_str, maxlen); > return isa_str; > } > > -- > 2.25.1 > > > --000000000000715d3105da67cce9 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Thu, Mar 17, 2022 at 1:58 AM Atish Pat= ra <atishp@rivosinc.com> w= rote:
The Linux kernel parses the ISA extensions from "risc= v,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.

Generate the extended ISA string by appending the available ISA extensions<= br> to the "riscv,isa" string if it is enabled so that kernel can pro= cess it.

[1] https://lkml.org/lkml/2022/2/15/263

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Heiko Stubner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes from v5->v6:
1. Improved commit message.
2. Fixed a typo for Zfh.

Changes from v4->v5:
1. Fixed the order of Zxx extensions.
2. Added a comment clearly describing the rules of extension order.

Changes from v3->v4:
1. Fixed the order of the extension names.
2. Added all the available ISA extensions in Qemu.

Changes from v2->v3:
1. Used g_strconcat to replace snprintf & a max isa string length as suggested by Anup.
2. I have not included the Tested-by Tag from Heiko because the
implementation changed from v2 to v3.

Changes from v1->v2:
1. Improved the code redability by using arrays instead of individual check=
---
=C2=A0target/riscv/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++= +
=C2=A01 file changed, 60 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ffb7..937ccdda997b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@

=C2=A0/* RISC-V CPU definitions */

+struct isa_ext_data {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 const char *name;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool enabled;

<= div>Nit: Should be 4 spaces indent.

Regards,
=
Frank Chang
=C2=A0
+};
+
=C2=A0static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG= ";

=C2=A0const char * const riscv_int_regnames[] =3D {
@@ -898,6 +903,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data)
=C2=A0 =C2=A0 =C2=A0device_class_set_props(dc, riscv_cpu_properties);
=C2=A0}

+#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
+
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len)
+{
+=C2=A0 =C2=A0 char *old =3D *isa_str;
+=C2=A0 =C2=A0 char *new =3D *isa_str;
+=C2=A0 =C2=A0 int i;
+
+=C2=A0 =C2=A0 /**
+=C2=A0 =C2=A0 =C2=A0* Here are the ordering rules of extension naming defi= ned by RISC-V
+=C2=A0 =C2=A0 =C2=A0* specification :
+=C2=A0 =C2=A0 =C2=A0* 1. All extensions should be separated from from othe= r multi-letter
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 extensions by an underscore.
+=C2=A0 =C2=A0 =C2=A0* 2. The first letter following the 'Z' conven= tionally indicates the most
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 closely related alphabetical extension = category, IMAFDQLCBKJTPVH.
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 If multiple 'Z' extensions are = named, they should be ordered first
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 by category, then alphabetically within= a category.
+=C2=A0 =C2=A0 =C2=A0* 3. Standard supervisor-level extensions (starts with= 'S') should be
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 listed after standard unprivileged exte= nsions.=C2=A0 If multiple
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 supervisor-level extensions are listed,= they should be ordered
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 alphabetically.
+=C2=A0 =C2=A0 =C2=A0* 4. Non-standard extensions (starts with 'X')= must be listed after all
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 standard extensions. They must be separ= ated from other multi-letter
+=C2=A0 =C2=A0 =C2=A0*=C2=A0 =C2=A0 extensions by an underscore.
+=C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 struct isa_ext_data isa_edata_arr[] =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zfh, ext_zfh),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zfinx, ext_zfinx),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zdinx, ext_zdinx),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zba, ext_zba),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zbb, ext_zbb),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zbc, ext_zbc),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zbs, ext_zbs),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zve32f, ext_zve32f),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zhinx, ext_zhinx),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(svinval, ext_svinval),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(svnapot, ext_svnapot),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+=C2=A0 =C2=A0 };
+
+=C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (isa_edata_arr[i].enabled) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 new =3D g_strconcat(old, "_= ", isa_edata_arr[i].name, NULL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_free(old);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 old =3D new;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 *isa_str =3D new;
+}
+
=C2=A0char *riscv_isa_string(RISCVCPU *cpu)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int i;
@@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0*p =3D '\0';
+=C2=A0 =C2=A0 riscv_isa_string_ext(cpu, &isa_str, maxlen);
=C2=A0 =C2=A0 =C2=A0return isa_str;
=C2=A0}

--
2.25.1


--000000000000715d3105da67cce9--